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參數(shù)資料
| 型號(hào)： | MC3100EP33DT |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 諧振器 |
| 英文描述： | 100E SERIES, PRESCALER, PDSO8 |
| 封裝： | PLASTIC, TSSOP-8 |
| 文件頁(yè)數(shù)： | 1/11頁(yè) |
| 文件大?。?/td> | 175K |
| 代理商： | MC3100EP33DT |
Semiconductor Components Industries, LLC, 2006
January, 2006 Rev. 7
1
Publication Order Number:
MC10EP33/D
MC10EP33, MC100EP33
3.3V / 5VECL B4 Divider
Description
The MC10/100EP33 is an integrated
B4 divider. The differential
clock inputs.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
The reset pin is asynchronous and is asserted on the rising edge.
Upon powerup, the internal flipflops will attain a random state; the
reset allows for the synchronization of multiple EP33’s in a system.
The 100 Series contains temperature compensation.
Features
320 ps Propagation Delay
Maximum Frequency > 4 GHz Typical
PECL Mode Operating Range: VCC = 3.0 V to 5.5 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = 3.0 V to 5.5 V
Open Input Default State
Safety Clamp on Inputs
Q Output Will Default LOW with Inputs Open or at VEE
VBB Output
PbFree Packages are Available
*For additional marking information, refer to
Application Note AND8002/D.
H
= MC10
A = Assembly Location
K
= MC100 L
= Wafer Lot
5Q = MC10
Y = Year
3L
= MC100 W = Work Week
D = Date Code
G
= PbFree Package
(Note: Microdot may be in either location)
ALYWG
G
HP33
ALYWG
G
KP33
MARKING
DIAGRAMS*
SOIC8
D SUFFIX
CASE 751
TSSOP8
DT SUFFIX
CASE 948R
1
8
1
8
1
8
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
ORDERING INFORMATION
http://onsemi.com
1
8
HEP33
ALYWG
G
1
8
KEP11
ALYWG
G
1
8
DFN8
MN SUFFIX
CASE 506AA
5Q
D
G
14
3L
D
G
14
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