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參數(shù)資料
| 型號： | MC3100EP16VSDTG |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 通用總線功能 |
| 英文描述： | 3.3V / 5V ECL Differential Receiver/Driver with Variable Output Swing |
| 中文描述： | LINE TRANSCEIVER, PDSO8 |
| 封裝： | LEAD FREE, PLASTIC, TSSOP-8 |
| 文件頁數(shù)： | 1/12頁 |
| 文件大?。?/td> | 172K |
| 代理商： | MC3100EP16VSDTG |
Semiconductor Components Industries, LLC, 2006
December, 2006
Rev. 5
1
Publication Order Number:
MC100EP16VS/D
MC100EP16VS
3.3V / 5VECL Differential
Receiver/Driver with
Variable Output Swing
Description
The MC100EP16VS is a differential receiver with variable output
amplitude. The device is functionally equivalent to the 100EP16 with
an input pin that controls the amplitude of the outputs.
The V
CTRL
input pin controls the output amplitude of the EP16VS
and is referenced to V
CC
. (See Figure 4.) The operational range of the
V
CTRL
input is from
≤
V
BB
(max output amplitude) to V
CC
(min
output amplitude). (See Figure 3.) A variable resistor between the V
CC
and V
BB
pins, with the wiper driving V
CTRL
, can control the output
amplitude. Typical application circuits and a V
CTRL
Voltage vs.
Output Amplitude graph are described in this data sheet. When left
open, the V
CTRL
pin will be internally pulled down to V
EE
and operate
as a standard EP16, with 100% output amplitude.
The V
BB
pin, an internally generated voltage supply, is available to
this device only. For single
ended input conditions, the unused
differential input is connected to V
BB
as a switching reference voltage.
V
BB
may also rebias AC coupled inputs. When used, decouple V
BB
and V
CC
via a 0.01 F capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, V
BB
should be left open.
Features
220 ps Propagation Delay
Maximum Frequency
>
4 GHz Typical (See Graph)
The 100 Series Contains Temperature Compensation
PECL Mode Operating Range: V
CC
= 3.0 V to 5.5 V
with V
EE
= 0 V
NECL Mode Operating Range: V
CC
= 0 V
with V
EE
=
3.0 V to
5.5 V
Open Input Default State
Q Output Will Default LOW with Inputs Open or at V
EE
Pb
Free Packages are Available
*For additional marking information, refer to
Application Note AND8002/D.
A
L
Y
W
M
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Date Code
= Pb
Free Package
ALYW
KP62
MARKING
DIAGRAMS*
SOIC
8
D SUFFIX
CASE 751
TSSOP
8
DT SUFFIX
CASE 948R
1
8
1
8
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
ORDERING INFORMATION
http://onsemi.com
1
8
KEP62
ALYW
1
8
DFN8
MN SUFFIX
CASE 506AA
3
1
4
(Note: Microdot may be in either location)
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