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參數(shù)資料
| 型號： | MC28U512HACA-0QC00 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | MultiMediaCard Specification |
| 中文描述： | 多媒體卡規(guī)格 |
| 文件頁數(shù)： | 44/66頁 |
| 文件大?。?/td> | 1422K |
| 代理商： | MC28U512HACA-0QC00 |
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MultiMediaCard
TM
44
3 = stby
4 = tran
5 = data
6 = rcv
7 = prg
8 = dis
9–15 = reserved
‘0’ = not ready
‘1’ = ready
Permanently 0
‘0’ = disabled
‘1’ = enabled
8
EADY_FOR_DATA
SX
corresponds to buffer empty signaling on
the bus
A
7:6
5
reserved
APP_CMD
SR
The card will expect ACMD or indication
that the command has been interpreted
as ACMD.
C
4
3:2
1:0
4.9.8 Command Response Timings
All timing diagrams use the following schematics and abbreviations:
S
Start bit (= ‘0’)
T
Transmitter bit (Host = ‘1’, Card = ‘0’)
P
One-cycle pull-up (= ‘1’)
E
End bit (=1)
Z
High impedance state (-> = ‘1’)
D
Data bits
*
Repetition
CRC
Cyclic redundancy check bits (7 bits for command or
response, 16 bits for block data)
Card active
Host active
The difference between the P-bit and Z-bit is that a P-bit is actively driven to HIGH by the card
respectively host output driver, while Z-bit is driven to (respectively kept) HIGH by the pull-up resistors
R
CMD
respectively R
DAT
. Actively driven P-bits are less sensitive to noise superposition.
Timing Values
Min
Max
NCR
2
64
NID
5
5
10*(TAAC*Fop+1
00*NSAC)
NRC
8
--
NCC
8
--
NWR
2
--
NST
2
2
The host command and the card response are clocked out with the rising edge of the host clock. The
delay between host command and card response is NCR clock cycles. The following timing diagram is
relevant for host command CMD3 :
reserved
reserved for application specific commands
reserved for manufacturer test mode
Permanently 0
Unit
Clock cycles
Clock cycles
NAC
2
Clock cycles
Clock cycles
Clock cycles
Clock cycles
Clock cycles
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