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參數(shù)資料
| 型號(hào)： | MC26LS30DR2G |
| 廠商： | ON Semiconductor |
| 文件頁(yè)數(shù)： | 11/14頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DRIVER LINE CONFIG 16SOIC |
| 產(chǎn)品變化通告： | Product Obsolescence 24/Jan/2011 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類(lèi)型： | 驅(qū)動(dòng)器 |
| 驅(qū)動(dòng)器/接收器數(shù)： | 4/0 |
| 規(guī)程： | RS422，RS423 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC |
| 包裝： | 剪切帶 (CT) |
| 其它名稱(chēng)： | MC26LS30DR2GOSCT |
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MC26LS30
http://onsemi.com
6
Figure 4. Differential Mode Enable Timing
NOTES:
1. S.G. set to: f
p 1.0 MHz; duty cycle = 50%; tr, tf, p 10 ns.
2. Above tests conducted by monitoring output current levels.
Figure 5. SingleEnded Mode Rise/Fall Time and Data Propagation Delay
NOTES:
1. S.G. set to: f
p 100 kHz; duty cycle = 50%; tr, tf, p10 ns.
2. tSK4 = tPDHtPDL for each driver.
3. tSK5 computed by subtracting the shortest tPDH from the longest tPDH of the 4 drivers within a package.
4. tSK6 computed by subtracting the shortest tPDL from the longest tPDL of the 4 drivers within a package.
VEE
tPZH
tPZL
tPLZ
tPHZ
1.5 V
Output
Current
(Vin = Lo)
0.1 VSS/RL
VSS/RL
0.5 VSS/RL
RL
0 or 3.0 V
En
VSS
500 pF
450
S.G.
VCC
450
CC
+3.0 V
1.5 V
0 V
Vin
VCC
Vin
+2.5 V
S.G.
500 pF
VO
(Vin = Hi)
Vin
1.5 V
Vout
10%
50%
90%
tr
1.5 V
90%
0 V
10%
Vin
50%
tf
tPDL
tPDH
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