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參數(shù)資料
| 型號： | MC14LC5480ENR2 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 5/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CODEC-FILTER PCM 5V 20-SSOP |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 類型： | PCM 編解碼器/濾波器 |
| 數(shù)據(jù)接口： | PCM 音頻接口 |
| 分辨率（位）： | 13 b |
| ADC / DAC 數(shù)量： | 1 / 1 |
| 三角積分調(diào)變： | 無 |
| 電壓 - 電源，數(shù)字： | 4.5 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-SSOP |
| 包裝： | 帶卷 (TR) |
DIGITAL SWITCHING CHARACTERISTICS, LONG FRAME SYNC AND SHORT FRAME SYNC
(VDD = + 5 V ± 5%, VSS = 0 V, All Digital Signals Referenced to VSS, TA = – 40 to + 85°C, CL = 150 pF, Unless Otherwise Noted)
Ref.
No.
Characteristics
Min
Typ
Max
Unit
1
Master Clock Frequency for MCLK
—
256
512
1536
1544
2048
2560
4096
—
kHz
1
MCLK Duty Cycle for 256 kHz Operation
45
—
55
%
2
Minimum Pulse Width High for MCLK (Frequencies of 512 kHz or Greater)
50
—
ns
3
Minimum Pulse Width Low for MCLK (Frequencies of 512 kHz or Greater)
50
—
ns
4
Rise Time for All Digital Signals
—
50
ns
5
Fall Time for All Digital Signals
—
50
ns
6
Setup Time from MCLK Low to FST High
50
—
ns
7
Setup Time from FST High to MCLK Low
50
—
ns
8
Bit Clock Data Rate for BCLKT or BCLKR
64
—
4096
kHz
9
Minimum Pulse Width High for BCLKT or BCLKR
50
—
ns
10
Minimum Pulse Width Low for BCLKT or BCLKR
50
—
ns
11
Hold Time from BCLKT (BCLKR) Low to FST (FSR) High
20
—
ns
12
Setup Time for FST (FSR) High to BCLKT (BCLKR) Low
80
—
ns
13
Setup Time from DR Valid to BCLKR Low
0
—
ns
14
Hold Time from BCLKR Low to DR Invalid
50
—
ns
LONG FRAME SPECIFIC TIMING
15
Hold Time from 2nd Period of BCLKT (BCLKR) Low to FST (FSR) Low
50
—
ns
16
Delay Time from FST or BCLKT, Whichever is Later, to DT for Valid MSB Data
—
60
ns
17
Delay Time from BCLKT High to DT for Valid Chord and Step Bit Data
—
60
ns
18
Delay Time from the Later of the 8th BCLKT Falling Edge, or the Falling Edge
of FST to DT Output High Impedance
10
—
60
ns
19
Minimum Pulse Width Low for FST or FSR
50
—
ns
SHORT FRAME SPECIFIC TIMING
20
Hold Time from BCLKT (BCLKR) Low to FST (FSR) Low
50
—
ns
21
Setup Time from FST (FSR) Low to MSB Period of BCLKT (BCLKR) Low
50
—
ns
22
Delay Time from BCLKT High to DT Data Valid
10
—
60
ns
23
Delay Time from the 8th BCLKT Low to DT Output High Impedance
10
—
60
ns
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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| MC14LC5540DW | 功能描述:IC CODEC ADPCM 28-SOIC W RoHS:否 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比，標(biāo)準(zhǔn) ADC / DAC (db):81.5 / 88 動態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR) |
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