參數(shù)資料
型號(hào): MC14569BDW
廠商: MOTOROLA INC
元件分類: 通用總線功能
英文描述: Programmable Divide-By-N Dual 4-Bit Binary/BCD Down Counter
中文描述: 4000/14000/40000 SERIES, ASYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16
封裝: PLASTIC, SOIC-16
文件頁(yè)數(shù): 3/12頁(yè)
文件大?。?/td> 323K
代理商: MC14569BDW
MOTOROLA CMOS LOGIC DATA
3
MC14569B
Characteristic
Symbol
Vdc
Unit
VDD
Min
Typ #
Max
Output Rise Time
tTLH
5.0
10
15
100
50
40
200
100
80
ns
Output Fall Time
tTHL
5.0
10
15
100
50
40
200
100
80
ns
Turn–On Delay Time
Zero Detect Output
tPLH
5.0
10
15
420
175
125
700
300
250
ns
Q Output
5.0
10
15
675
285
200
1200
500
400
ns
Turn–Off Delay Time
Zero Detect Output
tPHL
5.0
10
15
380
150
100
600
300
200
ns
Q Output
5.0
10
15
530
225
155
1000
400
300
ns
Clock Pulse Width
tWH
5.0
10
15
300
150
115
100
45
30
ns
Clock Pulse Frequency
fcl
5.0
10
15
3.5
9.5
13.0
2.1
5.1
7.8
MHz
Clock Pulse Rise and Fall Time
tTLH, tTHL
5.0
10
15
NO LIMIT
μ
s
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
SWITCHING WAVEFORMS
tWH
Figure 1.
Figure 2.
20 ns
20 ns
CLOCK
Q
CLOCK
ZERO DETECT
90%
50%
10%
50%
90%
10%
tPLH
tPHL
20 ns
20 ns
90%
50%
10%
tWH
tPLH
tPHL
90%
10%
tTLH
tTHL
tTLH
tTHL
fin = fmax
相關(guān)PDF資料
PDF描述
MC14569BCL Programmable Divide-By-N Dual 4-Bit Binary/BCD Down Counter
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