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參數資料
| 型號： | MC14562BCL |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | 128-Bit Static Shift Register |
| 中文描述： | 4000/14000/40000 SERIES, 128-BIT RIGHT SERIAL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, CDIP14 |
| 封裝： | CERAMIC, DIP-14 |
| 文件頁數： | 1/6頁 |
| 文件大小： | 183K |
| 代理商： | MC14562BCL |
MOTOROLA CMOS LOGIC DATA
Motorola, Inc. 1995
1
MC14562B
The MC14562B is a 128–bit static shift register constructed with MOS
P–channel and N–channel enhancement mode devices in a single
monolithic structure. Data is clocked in and out of the shift register on the
positive edge of the clock input. Data outputs are available every 16 bits,
from 16 through bit 128. This complementary MOS shift register is primarily
used where low power dissipation and/or high noise immunity is desired.
Diode Protection on All Inputs
Fully Static Operation
Cascadable to Provide Longer Shift Register Lengths
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low–power TTL Loads or One Low–power
VDD
Vin, Vout
Iin, Iout
DC Supply Voltage
– 0.5 to + 18.0
V
Input or Output Voltage (DC or Transient)
– 0.5 to VDD + 0.5
±
10
V
Input or Output Current (DC or Transient),
per Pin
mA
PD
Tstg
TL
Power Dissipation, per Package
500
mW
Storage Temperature
– 65 to + 150
C
Lead Temperature (8–Second Soldering)
260
C
* Maximum Ratings are those values beyond which damage to the device may occur.
Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C
LOGIC DIAGRAM
D
C
Q
1
D
C
Q
2
D
C
Q
3
D
C
Q
16
D
C
17
Q
D
C
32
Q
D
C
33
Q
D
C
48
Q
D
C
49
Q
D
C
64
Q
CLOCK 5
DATA IN 12
D
C
65
Q
D
C
Q
80
D
C
81
Q
D
C
Q
96
D
C
97
Q
D
C
112
Q
D
C
113
Q
D
C
128
Q
10 Q16
13 Q32
9
Q48
1
Q64
8
Q80
2
Q96
6
Q112
3
Q128
SEMICONDUCTOR TECHNICAL DATA
REV 3
1/94
BLOCK DIAGRAM
L SUFFIX
CERAMIC
CASE 632
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
TA = – 55
°
to 125
°
C for all packages.
Plastic
Ceramic
SOIC
P SUFFIX
PLASTIC
CASE 646
D SUFFIX
SOIC
CASE 751A
10
13
9
1
8
2
6
3
Q128
Q112
Q96
Q80
Q64
Q48
Q32
Q16
12
5
DATA
CLOCK
VDD = PIN 14
VSS = PIN 7
Pins 4 and 11
not used.
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