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參數(shù)資料
| 型號： | MC14557 |
| 廠商： | ON SEMICONDUCTOR |
| 英文描述： | 1-to-64 Bit Variable Length Shift Register |
| 中文描述： | 1到64位可變長度移位寄存器 |
| 文件頁數(shù)： | 3/6頁 |
| 文件大?。?/td> | 203K |
| 代理商： | MC14557 |
MOTOROLA CMOS LOGIC DATA
3
MC14557B
Rise and Fall Time, Q or Q Output
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns
Propagation Delay, Clock or CE to Q or Q
tPLH, tPHL = (1.7 ns/pF) CL + 215 ns
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns
tPLH, tPHL = (0.5 ns/pF) CL + 65 ns
Propagation Delay, Reset to Q or Q
tPLH, tPHL = (1.7 ns/pF) CL + 215 ns
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns
tPLH, tPHL = (0.5 ns/pF) CL + 70 ns
Pulse Width, Clock
tWH(cl)
ns
tTLH,
tTHL
5
10
15
—
—
—
100
50
40
200
100
80
tPLH,
tPHL
5
10
15
—
—
—
300
130
90
600
260
180
ns
tPLH,
tPHL
5
10
15
5
10
15
5
10
15
5
10
15
—
—
—
200
100
75
300
140
100
—
—
—
300
130
95
95
45
35
150
70
50
3.0
7.5
13.0
600
260
190
—
—
—
—
—
—
1.7
5.0
6.7
ns
ns
Pulse Width, Reset
tWH(rst)
ns
Clock Frequency (50% Duty Cycle)
fcl
MHz
Setup Time, A or B to Clock or CE
Worst case condition: L1 = L2 = L4 = L8 =
L16 = L32 = VSS (Register Length = 1)
tsu
5
10
15
5
10
15
700
290
145
400
165
60
350
130
85
45
5
0
—
—
—
—
—
—
ns
Best case condition: L32 = VDD, L1 through L16 =
Don’t Care (Any register length from 33 to 64)
Hold Time, Clock or CE to A or B
Best case condition: L1 = L2 = L4 = L8 = L16 =
L32 = VSS (Register Length = 1)
th
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
200
100
10
400
185
85
– 150
– 60
– 50
50
25
22
—
—
—
—
—
—
ns
Worst case condition: L32 = VDD, L1 through L16 =
Don’t Care (Any register length from 33 to 64)
Rise and Fall Time, Clock
tr,
tf
No Limit
—
Rise and Fall Time, Reset or CE
tr,
tf
—
—
—
160
80
70
—
—
—
80
40
35
15
5
4
—
—
—
μ
s
Removal Time, Reset to Clock or CE
trem
ns
*The formulas given are for the typical characteristics only at 25 C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
TIMING DIAGRAM
1–bit length:
CE = 0
A/B = 1
L1 = L2 = L4 = L8 = L16 = L32 = 0
PWR
50%
tWH(cl)
th
50%
tsu
trem
50%
tTLH
tTHL
tPHL
tPHL
tPLH
90%
50%
10%
A INPUT
CLOCK
RESET
Q
VDD
VSS
VDD
VSS
VDD
VSS
VOH
VOL
1/fcl
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