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參數(shù)資料
| 型號： | MC145572APB |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 22/52頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ISDN INTERFACE TXCVER 44-LQFP |
| 標(biāo)準(zhǔn)包裝： | 160 |
| 類型： | 收發(fā)器 |
| 規(guī)程： | RS232 |
| 電源電壓： | 5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-LQFP |
| 供應(yīng)商設(shè)備封裝： | 44-LQFP（10x10） |
| 包裝： | 托盤 |
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MC145572EVK
30
LTSFAR: Receive Superframe Alignment.
This pin carries a signal that indicates the rst 2B+D frame in a U superframe to be received from the
U-Interface. This signal is not active when the LT side MC145572 is congured for full GCI mode operation.
When the LT side MC145572 is congured for full GCI mode operation, S2-5 in GCI position, this pin
provides the recovered timing clock. The frequency of the clock is selected between 2.048 MHz and
512 kHz by the setting of S2-4, GCI2048/GCI512.
LTGTCLK: Gated IDL Clock Output.
This pin provides a gated clock output. The clock input of an external bit error rate tester should be
connected to this signal.
GND: Ground.
Negative Power Supply.
Table 2-5. NT and LT Side MC145572EVK Header List
Header
Reference
Function
J1
Access to LT Test Signals
J2
Access to LT 2B1Q Signal
J3
Short Positive Side of the Line to Ground
J4
Short Negative Side of the Line to Ground
J5
Tx/Rx Headers
J6
Access to LT TDM Signals
J7
LT RxDATA
J8
LT TxDATA
J9
Access to Multifunction MC145572 Pins
J10
LT CLK
J11
Access to Multifunction Pins
J12
Access to NT 2B1Q Signal
J13
Short Positive Side of the Line to Ground
J14
Short Negative Side of the Line to Ground
J15
Tx/Rx Header Pins
J17
Access to NT TDM Signals
J18
NT RxDATA
J19
Power Connector
J20
NT TxDATA
J21
NT CLK
J22
NT Data Interface Signals
J23
Access to SIT 2B1Q TE
J24
Access to SIT 2B1Q NT
JP1
LT PWR CONFIG
JP2
Short Line
JP3
Short R1
JP4
Short LT Sealing Current Blocking Cap
JP5
Short R6
JP6
Terminate Line with 135
W
JP7
Short Line
JP8
Short R17
JP9
Short N7 Sealing Current Blocking Cap
JP10
NT PWR CONFIG
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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