參數(shù)資料
型號(hào): MC14553BDW
廠商: ON SEMICONDUCTOR
元件分類: 通用總線功能
英文描述: Single Channel (1.5V) SVS with /MR in 5/SOT23 5-SOT-23 -40 to 85
中文描述: 4000/14000/40000 SERIES, SYN NEGATIVE EDGE TRIGGERED 12-BIT UP DECADE COUNTER, PDSO16
封裝: SOIC-16
文件頁(yè)數(shù): 5/12頁(yè)
文件大?。?/td> 178K
代理商: MC14553BDW
MC14553B
http://onsemi.com
5
Figure 1. 3–Digit Counter Timing Diagram (Reference Figure 3)
1
9
9
9
9
9
9
9
9
9
9
9
9
8
1
1
9
9
9
9
9
9
9
9
9
9
8
8
8
8
1
1
1
1
1
1
1
1
9
8
7
6
5
4
3
2
1
UNITS CLOCK
UNITS Q0
UNITS Q1
UNITS Q2
UNITS Q3
TENS CLOCK
TENS Q0
TENS Q3
HUNDREDS
CLOCK
HUNDREDS Q0
HUNDREDS Q3
DISABLE
OVERFLOW
MASTER
RESET
SCAN
OSCILLATOR
DIGIT SELECT 1
DIGIT SELECT 2
DIGIT SELECT 3
UP AT 80
UP AT 980
UP AT 800
(DISABLES CLOCK WHEN HIGH)
UNITS
TENS
HUNDREDS
PULSE
GENERATOR
(a)
16
V
DD
Q3
Q2
Q1
Q0
O.F.
DS1
DS2
DS3
8
V
SS
C
LE
DIS
MR
C
L
C
L
C
L
C
L
C
L
GENERATOR
1
(b)
V
DD
Q3
Q2
Q1
Q0
O.F.
DS1
DS2
DS3
V
SS
C
LE
MR
DIS
C
L
C
L
C
L
C
L
C
L
GENERATOR
2
GENERATOR
3
20 ns
20 ns
90%
10%
t
PLH
t
PHL
50%
50%
t
THL
t
TLH
10%
90%
50%
1/f
cl
t
PHL
t
WL(cl)
9
1
t
TLH
50%
OVERFLOW
BCD OUT
CLOCK
90%
10%
t
rem
t
PHL
, t
PLH
50%
50%
50%
t
WH(R)
t
su
t
PHL
MASTER RESET
BCD OUT
LATCH
ENABLE
CLOCK
Figure 2. Switching Time Test Circuits and Waveforms
t
su
相關(guān)PDF資料
PDF描述
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