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參數(shù)資料
| 型號： | MC14541BFR2 |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 時鐘/數(shù)據(jù)恢復(fù)及定時提取 |
| 英文描述： | 1 TIMER(S), PROGRAMMABLE TIMER, PDSO14 |
| 封裝： | EIAJ, PLASTIC, SOIC-14 |
| 文件頁數(shù)： | 5/10頁 |
| 文件大小： | 163K |
| 代理商： | MC14541BFR2 |
MC14541B
http://onsemi.com
4
Characteristic
Symbol
VDD
Min
Typ
(Note 6)
Max
Unit
Output Rise and Fall Time
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns
tTLH,
tTHL
5.0
10
15
100
50
40
200
100
80
ns
Propagation Delay, Clock to Q (28 Output)
tPLH, tPHL = (1.7 ns/pF) CL + 3415 ns
tPLH, tPHL = (0.66 ns/pF) CL + 1217 ns
tPLH, tPHL = (0.5 ns/pF) CL + 875 ns
tPLH
tPHL
5.0
10
15
3.5
1.25
0.9
10.5
3.8
2.9
ms
Propagation Delay, Clock to Q (216 Output)
tPHL, tPLH = (1.7 ns/pF) CL + 5915 ns
tPHL, tPLH = (0.66 ns/pF) CL + 3467 ns
tPHL, tPLH = (0.5 ns/pF) CL + 2475 ns
tPHL
tPLH
5.0
10
15
6.0
3.5
2.5
18
10
7.5
ms
Clock Pulse Width
tWH(cl)
5.0
10
15
900
300
225
300
100
85
ns
Clock Pulse Frequency (50% Duty Cycle)
fcl
5.0
10
15
1.5
4.0
6.0
0.75
2.0
3.0
MHz
MR Pulse Width
tWH(R)
5.0
10
15
900
300
225
300
100
85
ns
Master Reset Removal Time
trem
5.0
10
15
420
200
210
100
ns
5. The formulas given are for the typical characteristics only at 25_C.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
Figure 1. Power Dissipation Test Circuit
and Waveform
Figure 2. Switching Time Test Circuit
and Waveforms
PULSE
GENERATOR
VDD
CL
Q
RS
AR
Q/Q SELECT
MODE
A
B
MR
VSS
20 ns
90% 50%
10%
50%
DUTY CYCLE
(Rtc AND Ctc OUTPUTS ARE LEFT OPEN)
PULSE
GENERATOR
VDD
RS
Q/Q SELECT
MODE
A
B
MR
VSS
CL
Q
20 ns
90% 50%
20 ns
10%
RS
Q
tPLH
50%
90%
50%
10%
50%
tTLH
tTHL
tPHL
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