參數資料
| 型號： | MC14536BFEL |
| 廠商： | ON Semiconductor |
| 文件頁數： | 10/14頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OSC PROG TIMER 2MHZ 16SOEIAJ |
| 產品變化通告： | Product Obsolescence 24/Jan/2011 |
| 標準包裝： | 2,000 |
| 類型： | 可編程計時器 |
| 頻率： | 2MHz |
| 電源電壓： | 3 V ~ 18 V |
| 電流 - 電源： | 15µA |
| 工作溫度： | -55°C ~ 125°C |
| 封裝/外殼： | 16-SOIC（0.209"，5.30mm 寬） |
| 包裝： | 帶卷 (TR) |
| 供應商設備封裝： | 16-SOEIAJ |
| 安裝類型： | 表面貼裝 |
MC14536B
http://onsemi.com
5
PIN DESCRIPTIONS
INPUTS
SET (Pin 1) A high on Set asynchronously forces Decode
Out to a high level. This is accomplished by setting an output
conditioning latch to a high level while at the same time
resetting the 24 flipflop stages. After Set goes low (inactive),
the occurrence of the first negative clock transition on IN1
causes Decode Out to go low. The counter’s flipflop stages
begin counting on the second negative clock transition of IN1.
When Set is high, the onchip RC oscillator is disabled. This
allows for very lowpower standby operation.
RESET (Pin 2) A high on Reset asynchronously forces
Decode Out to a low level; all 24 flipflop stages are also reset
to a low level. Like the Set input, Reset disables the onchip
RC oscillator for standby operation.
IN1 (Pin 3) The device’s internal counters advance on the
negativegoing edge of this input. IN1 may be used as an
external clock input or used in conjunction with OUT1 and
OUT2 to form an RC oscillator. When an external clock is
used, both OUT1 and OUT2 may be left unconnected or used
to drive 1 LSTTL or several CMOS loads.
8BYPASS (Pin 6) A high on this input causes the first 8
flipflop stages to be bypassed. This device essentially
becomes a 16stage counter with all 16 stages selectable.
Selection is accomplished by the A, B, C, and D inputs. (See
the truth tables.)
CLOCK INHIBIT (Pin 7) A high on this input
disconnects the first counter stage from the clocking source.
This holds the present count and inhibits further counting.
However, the clocking source may continue to run.
Therefore, when Clock Inhibit is brought low, no oscillator
startup time is required. When Clock Inhibit is low, the
counter will start counting on the occurrence of the first
negative edge of the clocking source at IN1.
OSC INHIBIT (Pin 14) A high level on this pin stops the
RC oscillator which allows for very lowpower standby
operation. May also be used, in conjunction with an external
clock, with essentially the same results as the Clock Inhibit
input.
MONOIN (Pin 15) Used as the timing pin for the
onchip monostable multivibrator. If the MonoIn input is
connected to VSS, the monostable circuit is disabled, and
Decode Out is directly connected to the selected Q output.
The monostable circuit is enabled if a resistor is connected
between MonoIn and VDD. This resistor and the device’s
internal capacitance will determine the minimum output
pulse widths. With the addition of an external capacitor to
VSS, the pulse width range may be extended. For reliable
operation the resistor value should be limited to the range of
5 k
W to 100 kW and the capacitor value should be limited to
A, B, C, D (Pins 9, 10, 11, 12) These inputs select the
flipflop stage to be connected to Decode Out. (See the truth
tables.)
OUTPUTS
OUT1, OUT2 (Pin 4, 5) Outputs used in conjunction with
IN1 to form an RC oscillator. These outputs are buffered and
may be used for 20 frequency division of an external clock.
DECODE OUT (Pin 13) Output function depends on
configuration. When the monostable circuit is disabled, this
output is a 50% duty cycle square wave during free run.
TEST MODE
The test mode configuration divides the 24 flipflop
stages into three 8stage sections to facilitate a fast test
sequence. The test mode is enabled when 8Bypass, Set and
Reset are at a high level. (See Figure 10.)
TRUTH TABLES
Input
Stage Selected
for Decode Out
8Bypass
D
C
B
A
0
9
0
1
10
0
1
0
11
0
1
12
0
1
0
13
0
1
0
1
14
0
1
0
15
0
1
16
0
1
0
17
0
1
0
1
18
0
1
0
1
0
19
0
1
0
1
20
0
1
0
21
0
1
0
1
22
0
1
0
23
0
1
24
Input
Stage Selected
for Decode Out
8Bypass
D
C
B
A
1
0
1
0
1
2
1
0
1
0
3
1
0
1
4
1
0
1
0
5
1
0
1
0
1
6
1
0
1
0
7
1
0
1
8
1
0
9
1
0
1
10
1
0
1
0
11
1
0
1
12
1
0
13
1
0
1
14
1
0
15
1
16
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