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參數(shù)資料
| 型號： | MC145193F |
| 廠商： | MOTOROLA INC |
| 元件分類： | XO, clock |
| 英文描述： | 1.1 GHZ PLL FREQUENCY SYNTHESIZER |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 1100 MHz, PDSO20 |
| 封裝： | PLASTIC, SO-20 |
| 文件頁數(shù)： | 22/24頁 |
| 文件大?。?/td> | 240K |
| 代理商： | MC145193F |
M
2
M
S
1
2
7
8
9
15
16
17
23
24
25
R Register Bits of Device #2
in Figure 22
R Register Bits of Device #1
in Figure 22
R15
R14
R8
R7
R0
X
X
R15
31
32
33
39
40
R8
R7
R0
Note 1 Note 2
F
ENB
CLK
Din
1. At this point, bits R13, R14 and R15 are stored and sent to the ‘‘OSC or 4–Stage Divider” block in the Block Diagram. Bits R0 through
R12 are loaded into the first buffer in the double–buffered section of the R register. Therfore, the R counter divide is not altered yet and
retains the previous ratio loaded. The C and A registers are not affected.
2. Optional load pulse. At this point, the bits R0 through R12 are transfered to the second buffer of the R register. The R counter begins dividing
by the new ratio after completing the rest of the present count cycle. CLK must be low during the ENB pulse, as shown. The C and A registers
are not affected. The first buffer of the R register is not affected. Also, see note of Figure 24 for an alternate method of loading the second
buffer in the R register.
Notes Applicable to Each Device:
Figure 25. Accessing the R Registers of Two Cascaded
MC145193 or MC145202–1 Devices
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| MC14519BCL | 制造商:Motorola Inc 功能描述: 制造商:Motorola Inc 功能描述:LOGIC MUX, QUAD, 2-INPUT, CMOS, 16 Pin, Ceramic, DIP |
| MC14519BD | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC14519BF | 制造商:Panasonic Industrial Company 功能描述:IC |
| MC1451CCP | 制造商:PMD 功能描述: |
| MC14520B | 制造商:Motorola Inc 功能描述: 制造商:ON Semiconductor 功能描述: |
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