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| 型號： | MC14516BDR2G |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 1/10頁 |
| 文件大小： | 0K |
| 描述： | IC COUNTER BINARY UP/DOWN 16SOIC |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | 4000B |
| 邏輯類型： | 二進(jìn)制計(jì)數(shù)器 |
| 方向： | 上，下 |
| 元件數(shù)： | 1 |
| 每個(gè)元件的位元數(shù)： | 4 |
| 復(fù)位： | 異步 |
| 計(jì)時(shí)： | 同步 |
| 計(jì)數(shù)速率： | 8MHz |
| 觸發(fā)器類型： | 正邊沿 |
| 電源電壓： | 3 V ~ 18 V |
| 工作溫度： | -55°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | MC14516BDR2GOSDKR |
Semiconductor Components Industries, LLC, 2014
March, 2014 Rev. 10
1
Publication Order Number:
MC14516B/D
MC14516B
Binary Up/Down Counter
The MC14516B synchronous up/down binary counter is
constructed with MOS Pchannel and Nchannel enhancement mode
devices in a monolithic structure.
This counter can be preset by applying the desired value, in binary,
to the Preset inputs (P0, P1, P2, P3) and then bringing the Preset
Enable (PE) high. The direction of counting is controlled by applying
a high (for up counting) or a low (for down counting) to the
UP/DOWN input. The state of the counter changes on the positive
transition of the clock input.
Cascading can be accomplished by connecting the Carry Out to the
Carry In of the next stage while clocking each counter in parallel. The
outputs (Q0, Q1, Q2, Q3) can be reset to a low state by applying a high
to the reset (R) pin.
This CMOS counter finds primary use in up/down and difference
counting. Other applications include: (1) Frequency synthesizer
applications where low power dissipation and/or high noise immunity
is desired, (2) AnalogtoDigital and DigitaltoAnalog conversions,
and (3) Magnitude and sign generation.
Features
Diode Protection on All Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Internally Synchronous for High Speed
Logic EdgeClocked Design — Count Occurs on Positive Going
Edge of Clock
Single Pin Reset
Asynchronous Preset Enable Operation
Capable of Driving Two LowPower TTL Loads or One
LowPower Schottky Load Over the Rated Temperature Range
These Devices are PbFree and are RoHS Compliant
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AECQ100
Qualified and PPAP Capable
MAXIMUM RATINGS (Voltages Referenced to VSS)
Parameter
Symbol
Value
Unit
DC Supply Voltage Range
VDD
0.5 to +18.0
V
Input or Output Voltage Range
(DC or Transient)
Vin, Vout
0.5 to VDD
+ 0.5
V
Input or Output Current (DC or Transient)
per Pin
Iin, Iout
±10
mA
Power Dissipation, per Package (Note 1)
PD
500
mW
Ambient Temperature Range
TA
55 to +125
°C
Storage Temperature Range
Tstg
65 to +150
°C
Lead Temperature (8Second Soldering)
TL
260
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating: Plastic “DW” Packages:
– 7.0 mW/
_C From 65_C To 125_C
This device contains protection circuitry to guard
against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated
voltages to this highimpedance circuit. For proper
operation, Vin and Vout should be constrained to the
range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate
logic voltage level (e.g., either VSS or VDD). Unused
outputs must be left open.
http://onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
ORDERING INFORMATION
A
= Assembly Location
WL
= Wafer Lot
Y
= Year
WW
= Work Week
G
= PbFree Package
MARKING
DIAGRAM
SOIC16
D SUFFIX
CASE 751B
1
16
14516BG
AWLYWW
1
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