
MC14511B
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5
Figure 1. Dynamic Power Dissipation Signal Waveforms
Input LE low, and Inputs D, BI and LT high.
f in respect to a system clock.
All outputs connected to respective C
L
loads.
20 ns
20 ns
V
DD
V
SS
V
OH
V
OL
90%
50%
1
2f
10%
50%
A, B, AND C
ANY OUTPUT
50% DUTY CYCLE
Figure 2. Dynamic Signal Waveforms
20 ns
20 ns
V
DD
90%
50%
10%
INPUT C
(a) Inputs D and LE low, and Inputs A, B, BI and LT high.
V
SS
V
OH
V
OL
OUTPUT g
t
PLH
t
PHL
90%
10%
50%
t
TLH
t
THL
(b) Input D low, Inputs A, B, BI and LT high.
20 ns
10%
90%
50%
V
DD
V
SS
V
DD
V
SS
V
OH
V
OL
t
h
t
su
50%
INPUT C
OUTPUT g
LE
(c) Data DCBA strobed into latches.
20 ns
20 ns
V
DD
V
SS
LE
90%
50%
10%
t
WL