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參數(shù)資料
| 型號： | MC14194BD |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | 4-Bit Bidirectional Universal Shift Register |
| 中文描述： | 4000/14000/40000 SERIES, 4-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16 |
| 封裝： | PLASTIC, SOIC-16 |
| 文件頁數(shù)： | 1/6頁 |
| 文件大?。?/td> | 239K |
| 代理商： | MC14194BD |
MOTOROLA CMOS LOGIC DATA
MC14194B
284
The MC14194B is a 4–bit static shift register capable of operating in the
parallel load, serial shift left, serial shift right, or hold mode. The
asynchronous Reset input, when at a low level, overrides all other inputs,
resets all stages, and forces all outputs low. When Reset is at a logic 1 level,
the two mode control inputs, S0 and S1, control the operating mode as
shown in the truth table. Both serial and parallel operation are triggered on
the positive–going transition of the Clock input. The Parallel Data, Data Shift,
and mode control inputs must be stable for the specified setup and hold
times before and after the positive–going Clock transition.
Synchronous Right/Left Serial Operation
Synchronous Parallel Load
Asynchronous Hold (Do Nothing) Mode
MAXIMUM RATINGS*
Symbol
Parameter
DC Supply Voltage
Value
– 0.5 to + 18.0
Unit
V
Input or Output Voltage (DC or Transient)
±
10
V
Input or Output Current (DC or Transient),
mA
PD
TL
Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C
Power Dissipation, per Package
500
mW
Lead Temperature (8–Second Soldering)
260
C
Q
LOGIC DIAGRAM
RESET
CLOCK
DSR
S0
S1
1
11
2
9
10
5
6
4
3
DP1
DP0
DP2
DP3
7
DSL
Q0
Q1
Q2
Q3
15
14
13
12
D
C
R
D Q
C
R
D Q
C
R
D Q
C
R
VDD = PIN 16
VSS = PIN 8
SEMICONDUCTOR TECHNICAL DATA
REV 3
1/94
L SUFFIX
CERAMIC
CASE 620
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
TA = – 55
°
to 125
°
C for all packages.
Plastic
Ceramic
SOIC
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
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