參數(shù)資料
型號： MC14175BF
廠商： ON SEMICONDUCTOR
元件分類： 通用總線功能
英文描述： Quad Type D Flip-Flop
中文描述： 4000/14000/40000 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16
封裝： EIAJ, SO-16
文件頁數(shù)： 1/8頁
文件大?。?/td> 173K
代理商： MC14175BF
Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 3
1
Publication Order Number:
MC14175B/D
The MC14175B quad type D flip–flop is constructed with MOS
P–channel and N–channel enhancement mode devices in a single
monolithic structure. Each of the four flip–flops is positive–edge
triggered by a common clock input (C). An active–low reset input (R)
asynchronously resets all flip–flops. Each flip–flop has independent
Data (D) inputs and complementary outputs (Q and Q). These devices
may be used as shift register elements or as type T flip–flops for
counter and toggle applications.
Complementary Outputs
Static Operation
All Inputs and Outputs Buffered
Diode Protection on All Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Output Compatible with Two Low–Power TTL Loads or One
Low–Power Schottky TTL Load
Functional Equivalent to TTL 74175
MAXIMUM RATINGS
(Voltages Referenced to V
SS
) (Note 2.)
Symbol
Parameter
Value
Unit
V
DD
DC Supply Voltage Range
–0.5 to +18.0
V
V
in
, V
out
Input or Output Voltage Range
(DC or Transient)
–0.5 to V
DD
+ 0.5
V
I
in
, I
out
Input or Output Current
(DC or Transient) per Pin
±
10
mA
P
D
Power Dissipation,
per Package (Note 3.)
500
mW
T
A
Ambient Temperature Range
–55 to +125
°
C
T
stg
Storage Temperature Range
–65 to +150
°
C
T
L
Lead Temperature
(8–Second Soldering)
260
°
C
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
(V
in
or V
out
)
V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V
SS
or V
DD
). Unused outputs must be left open.
http://onsemi.com
A
WL or L
YY or Y
WW or W = Work Week
= Assembly Location
= Wafer Lot
= Year
Device
Package
Shipping
ORDERING INFORMATION
MC14175BCP
PDIP–16
2000/Box
MC14175BD
SOIC–16
48/Rail
MC14175BDR2
SOIC–16
2500/Tape & Reel
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
MARKING
DIAGRAMS
16
1
PDIP–16
P SUFFIX
CASE 648
MC14175BCP
AWLYYWW
SOIC–16
D SUFFIX
CASE 751B
1
16
14175B
AWLYWW
SOEIAJ–16
F SUFFIX
CASE 966
1
16
MC14175B
AWLYWW
MC14175BF
SOEIAJ–16
See Note 1.
MC14175BFEL
SOEIAJ–16
See Note 1.
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