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參數(shù)資料
| 型號： | MC141556P |
| 廠商： | MOTOROLA INC |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PDIP28 |
| 封裝： | PLASTIC, DIP-28 |
| 文件頁數(shù)： | 17/18頁 |
| 文件大小： | 159K |
| 代理商： | MC141556P |
MC141556
8
MOTOROLA
COMMUNICATION PROTOCOL
IIC Communication Protocol
This is a two-wire serial communication link that is fully com-
patible with the IIC bus system. It consists of SDA bidirectional
data line and SCL clock input line. Data is sent from a transmitter
(master), to a receiver (slave) via the SDA line, and is synchro-
nized with a transmitter clock on the SCL line at the receiving
end. The maximum data rate is limited to 400kbps. The default
chip address is $70. Please refer to the IIC-Bus specification for
the detail timing requirement.
Operating Procedure
FIGURE 7. shows the IIC transmission format. The master ini-
tiates a transmission routine by generating a START condition,
followed by a slave address byte. Once the address is properly
identified, the slave will respond with an ACKNOWLEDGE signal
by pulling the SDA line LOW during the ninth SCL clock. Each
data byte which then follows must be eight bits long, plus the
ACKNOWLEDGE bit, to make up nine bits together. Appropriate
hub setting information can be downloaded sequentially. See
Data Transmission Format for details. In the cases of no AC-
KNOWLEDGE or completion of data transfer, the master will
generate a STOP condition to terminate the transmission rou-
tine.
Figure 7. IIC FORMAT
DATA TRANSMISSION FORMAT
After the proper identification by the receiving device, Mas-
ter is now ready to program MC141556 by transmitting the
configuration data. The configuration data is shown in Table2
Programmable Configuration Data. To complete the program-
ming sequence, all six bytes of data are needed to be trans-
mitted. The transmission sequence is defined in Table2 . An
ACKNOWLEDGE bit must be inserted between each byte of
data as shown in FIGURE 8.
DATA BYTES
ACK
STOP CONDITION
ACK
CHIP ADDRESS
SDA
SCL
START CONDITION
1
9
8
2–7
Table 2. Programmable Configuration Data
Figure 8. MC141556 Configuration Programming
Data
Transmission
Sequence
Bit
Description
Default Chip Address
1st Byte
ADDR6 ~ ADDR0
Default Chip Address BIT6 ~ BIT0
WRITE
0 = WRITE ENABLE
VendorID (Upper Byte)
2nd Byte
VID15 ~ VID8
VendorID BIT15 ~ BIT8
VendorID (Lower Byte)
3rd Byte
VID7 ~ VID0
VendorID BIT7 ~ BIT0
ProductID (Upper Byte)
4th Byte
PID15 ~ PID8
ProductID BIT15 ~ BIT8
ProductID (Lower Byte)
5th Byte
PID7 ~ PID0
ProductID BIT7 ~ BIT0
Configuration
6th Byte
X
BIT7: Don’t Care
X
BIT6: Don’t Care
SPWR
BIT5: 1 = Self-powered Mode
BIT5 : 0 = Bus-powered Mode
NumPORT
BIT4 :1 = 5 Downstream Ports
BIT4 : 0 = 4 Downstream Ports
GANG
BIT3 :1 = Ganged control
BIT3 : 0 = Individual control
DEB2 ~ DEB0
Debounce Select BIT2 ~ BIT0
These three bits are used to adjust the time interval
to confirm the over-current condition : (time base is
1ms)
000 = 0ms, 001 = 1ms, 010 = 2ms, 011 =3ms,
100 = 4ms, 101 = 5ms, 110 = 6ms, 111 = 7ms;
Default setting is 3ms (011)
ADDR6 ~
ADDR0
WRITE
ACK
VID15 ~
VID8
ACK
VID7 ~
VID0
ACK
PID15 ~
PID8
ACK
PID7 ~
PID0
ACK X X
SPW
R
Num-
PORT
GANG
DEB2 ~
DEB0
ACK
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