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參數資料
| 型號： | MC140XXBFEL |
| 廠商： | ON SEMICONDUCTOR |
| 英文描述： | CMOS SSI |
| 中文描述： | 小型工業(yè)的CMOS |
| 文件頁數： | 1/6頁 |
| 文件大小： | 82K |
| 代理商： | MC140XXBFEL |
Semiconductor Components Industries, LLC, 2005
February, 2005 Rev. 5
1
Publication Order Number:
MC14070B/D
MC14070B, MC14077B
CMOS SSI
Quad Exclusive “OR” and “NOR” Gates
The MC14070B quad exclusive OR gate and the MC14077B quad
exclusive NOR gate are constructed with MOS Pchannel and
Nchannel enhancement mode devices in a single monolithic
structure. These complementary MOS logic gates find primary use
where low power dissipation and/or high noise immunity is desired.
Features
Supply Voltage Range = 3.0 Vdc to 18 Vdc
All Outputs Buffered
Capable of Driving Two LowPower TTL Loads or One LowPower
Schottky TTL Load Over the Rated Temperature Range
Double Diode Protection on All Inputs
MC14070B Replacement for CD4030B and CD4070B Types
MC14077B Replacement for CD4077B Type
PbFree Packages are Available*
MAXIMUM RATINGS
(Voltages Referenced to V
SS
)
Symbol
Parameter
Value
Unit
V
DD
DC Supply Voltage Range
0.5 to +18.0
V
V
in
, V
out
Input or Output Voltage Range
(DC or Transient)
0.5 to V
DD
+ 0.5
V
I
in
, I
out
Input or Output Current
(DC or Transient) per Pin
±
10
mA
P
D
Power Dissipation, per Package
(Note 1)
500
mW
T
A
Ambient Temperature Range
55 to +125
°
C
T
stg
Storage Temperature Range
65 to +150
°
C
T
L
Lead Temperature
(8Second Soldering)
260
°
C
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
highimpedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
(V
in
or V
out
)
V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V
SS
or V
DD
). Unused outputs must be left open.
*For additional information on our PbFree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
http://onsemi.com
MARKING
DIAGRAMS
1
14
PDIP14
P SUFFIX
CASE 646
MC140xxBCP
AWLYYWW
SOIC14
D SUFFIX
CASE 751A
1
14
140xxB
AWLYWW
xx
A
WL, L
YY, Y
WW, W
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
SOEIAJ14
F SUFFIX
CASE 965
1
14
MC140xxB
AWLYWW
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
ORDERING INFORMATION
相關PDF資料 |
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|---|---|
| MC14070BCPG | CMOS SSI |
| MC14077BCPG | CMOS SSI |
| MC14070BD | CMOS SSI |
| MC14070BDG | CMOS SSI |
| MC14070BDR2 | CMOS SSI |
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