參數(shù)資料
型號(hào)： MC14099BDW
廠商： MOTOROLA INC
元件分類： 通用總線功能
英文描述： 8-Bit Addressable Latches
中文描述： 4000/14000/40000 SERIES, LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, PDSO16
封裝： SOIC-16
文件頁(yè)數(shù)： 1/9頁(yè)
文件大?。?/td> 287K
代理商： MC14099BDW
MOTOROLA CMOS LOGIC DATA
MC14099B MC14599B
246
The MC14099B and MC14599B are 8–bit addressable latches. Data is
entered in serial form when the appropriate latch is addressed (via address
pins A0, A1, A2) and write disable is in the low state. Chip enable must be
high for writing into MC14599B. For the MC14599B the data pin is a
bidirectional data port and for the MC14099B the input is a unidirectional
write only port. The Write/Read line controls this port in the MC14599B.
The data is presented in parallel at the output of the eight latches
independently of the state of Write Disable, Write/Read or Chip Enable.
A Master Reset capability is available on both parts.
Serial Data Input
Parallel Output
Master Reset
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low–power TTL Loads or One Low–Power
MC14099B pin for pin compatible with CD4099B
MAXIMUM RATINGS*
Symbol
Parameter
VDD
DC Supply Voltage
Vin, Vout
Input or Output Voltage (DC or Transient)
Value
– 0.5 to + 18.0
– 0.5 to VDD + 0.5
Unit
V
V
TL
* Maximum Ratings are those values beyond which damage to the device may occur.
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C
MC14099B
Storage Temperature
Lead Temperature (8–Second Soldering)
– 65 to + 150
260
C
C
MC14599B
13
14
15
16
9
10
11
12
5
4
3
2
1
8
7
6
Q3
Q4
Q5
Q6
VDD
Q0
Q1
Q2
WRITE
DISABLE
DATA
RESET
Q7
VSS
A2
A1
A0
A0
DATA
WRITE
DISABLE
RESET
Q7
VSS
CE
A2
A1
Q4
Q5
Q6
VDD
WRITE/
READ
Q0
Q1
Q2
Q3
14
15
16
17
18
10
11
12
13
5
4
3
2
1
9
8
7
6
PIN ASSIGNMENT
PIN ASSIGNMENT
CHIP ENABLE
WWRITE/READ
DATA
A0
A1
A2
RESET
10
4
3
2
5
6
7
DECODER
11
12
13
14
15
16
17
1
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
8
LATCHES
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
8
LATCHES
DECODER
5
6
7
WRITE DIDATA
A0
A1
A2
RESET
8
4
3
2
8
VDD = 18
VSS = 9
VDD = 16
VSS = 8
9
10
11
12
13
14
15
1
SEMICONDUCTOR TECHNICAL DATA
Motorola, Inc. 1995
REV 0
1/94
L SUFFIX
CERAMIC
CASE 620
ORDERING INFORMATION
MC14099BCP
MC14099BCL
MC14099BDW
TA = – 55
°
to 125
°
C for all packages.
Plastic
Ceramic
SOIC
P SUFFIX
PLASTIC
CASE 648
DW SUFFIX
SOIC
CASE 751G
L SUFFIX
CERAMIC
CASE 726
ORDERING INFORMATION
MC14599BCP
MC14599BCL
Plastic
Ceramic
P SUFFIX
PLASTIC
CASE 707
This device contains protection circuitry to
guard against damage due to high static
voltages or electric fields. However, pre-
cautions must be taken to avoid applications of
any voltage higher than maximum rated volt-
ages to this high–impedance circuit. For proper
operation, Vin and Vout should be constrained
to the range VSS
(Vin or Vout)
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either VSS
or VDD). Unused outputs must be left open.
VDD.
TA = – 55
°
to 125
°
C for all packages.
相關(guān)PDF資料
PDF描述
MC14599B Battery-Backup Supervisor for Low Power Processors 14-TSSOP -40 to 85
MC14599BCL 8-Bit Addressable Latches
MC14599BCP Battery-Backup Supervisor for Low Power Processors 14-TSSOP -40 to 85
MC14599BDW Battery-Backup Supervisor for Low Power Processor 10-MSOP -40 to 85
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