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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | MC14094BDR2 |
| 寤犲晢锛� | ON Semiconductor |
| 鏂囦欢闋佹暩(sh霉)锛� | 5/10闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC SHIFT REGSTR 8BIT CMOS 16SOIC |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 1 |
| 绯诲垪锛� | 4000B |
| 閭忚集椤炲瀷锛� | 绉讳綅瀵勫瓨鍣� |
| 杓稿嚭椤炲瀷锛� | 涓夋厠(t脿i) |
| 鍏冧欢鏁�(sh霉)锛� | 1 |
| 姣忓€�(g猫)鍏冧欢鐨勪綅鍏冩暩(sh霉)锛� | 8 |
| 鍔熻兘锛� | 涓茶鑷冲苟琛� |
| 闆绘簮闆诲锛� | 3 V ~ 18 V |
| 宸ヤ綔婧害锛� | -55°C ~ 125°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 16-SOIC锛�0.154"锛�3.90mm 瀵級 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 16-SOIC |
| 鍖呰锛� | 妯�(bi膩o)婧�(zh菙n)鍖呰 |
| 鍏跺畠鍚嶇ū锛� | MC14094BDR2OSDKR |
MC14094B
http://onsemi.com
4
Characteristic
Symbol
VDD
Vdc
Min
Typ (6)
Max
Unit
Output Rise and Fall Time
tTLH, tTHL = (1.35 ns/pF) CL + 33 ns
tTLH, tTHL = (0.6 ns/pF) CL + 20 ns
tTLH, tTHL = (0.4 ns/pF) CL + 20 ns
tTLH,
tTHL
5.0
10
15
100
50
40
200
100
80
ns
Propagation Delay Time (Figure 1)
Clock to Serial out QS
tPLH, tPHL = (0.90 ns/pF) CL + 305 ns
tPLH, tPHL = (0.36 ns/pF) CL + 107 ns
tPLH, tPHL = (0.26 ns/pF) C L + 82 ns
Clock to Serial out Q鈥橲
tPLH, tPHL = (0.90 ns/pF) CL + 350 ns
tPLH, tPHL = (0.36 ns/pF) CL + 149 ns
tPLH, tPHL = (0.26 ns/pF) CL + 62 ns
Clock to Parallel out
tPLH, tPHL = (0.90 ns/pF) CL + 375 ns
tPLH, tPHL = (0.35 ns/pF) CL + 177 ns
tPLH, tPHL = (0.26 ns/pF) CL + 122 ns
Strobe to Parallel out
tPLH, tPHL = (0.90 ns/pF) CL + 245 ns
tPLH, tPHL = (0.36 ns/pF) C L + 127 ns
tPLH, tPHL = (0.26 ns/pF) CL + 87 ns
Output Enable to Output
tPHZ, tPZL = (0.90 ns/pF) CL + 95 ns
tPHZ, tPZL = (0.36 ns/PF) CL + 57 ns
tPHZ, tPZL = (0.26 ns/pF) CL + 42 ns
tPLZ, tPZH = (0.90 ns/pF) CL + 180 ns
tPLZ, tPZH = (0.36 ns/pF) CL + 77 ns
tPLZ, tPZH = (0.26 ns/pF) CL + 57 ns
tPLH,
tPHL
5.0
10
15
350
125
95
600
250
190
ns
5.0
10
15
230
110
75
460
220
150
5.0
10
15
420
195
135
840
390
270
5.0
10
15
290
145
100
580
290
200
tPHZ,
tPZL
5.0
10
15
140
75
55
280
150
110
tPLZ,
tPZH
5.0
10
15
225
95
70
450
190
140
Setup Time
Data in to Clock
tsu
5.0
10
15
125
55
35
60
30
20
ns
Hold Time
Clock to Data
th
5.0
10
15
0
20
鈥� 40
鈥� 10
0
ns
Clock Pulse Width, High
tWH
5.0
10
15
200
100
83
100
50
40
ns
Clock Rise and Fall Time
tr(cl)
tf(cl)
5
10
15
15
5.0
4.0
ms
Clock Pulse Frequency
fcl
5.0
10
15
2.5
5.0
6.0
1.25
2.5
3.0
MHz
Strobe Pulse Width
tWL
5.0
10
15
200
80
70
100
40
35
ns
5. The formulas given are for the typical characteristics only at 25_C.
6. Data labelled 鈥淭yp鈥� is not to be used for design purposes but is intended as an indication of the IC鈥檚 potential performance.
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| MC14094BDR2G | 鍔熻兘鎻忚堪:瑷�(j矛)鏁�(sh霉)鍣ㄧЩ浣嶅瘎瀛樺櫒 3-18V 8-Bit Shift/Store RoHS:鍚� 鍒堕€犲晢:Texas Instruments 瑷�(j矛)鏁�(sh霉)鍣ㄩ鍨�: 瑷�(j矛)鏁�(sh霉)闋嗗簭:Serial to Serial/Parallel 闆昏矾鏁�(sh霉)閲�:1 灏佽 / 绠遍珨:SOIC-20 Wide 閭忚集绯诲垪: 閭忚集椤炲瀷: 杓稿叆绶氳矾鏁�(sh霉)閲�:1 杓稿嚭椤炲瀷:Open Drain 鍌虫挱寤堕伈鏅�(sh铆)闁�:650 ns 鏈€澶у伐浣滄韩搴�:+ 125 C 鏈€灏忓伐浣滄韩搴�:- 40 C 灏佽:Reel |
| MC14094BDR2G-CUT TAPE | 鍒堕€犲晢:ON 鍔熻兘鎻忚堪:MC14094B Series 8-Stage Shift/Store Register w/Tri - State Outputs - SOIC-16 |
| MC14094BDTR2 | 鍔熻兘鎻忚堪:瑷�(j矛)鏁�(sh霉)鍣ㄧЩ浣嶅瘎瀛樺櫒 3-18V 8-Bit RoHS:鍚� 鍒堕€犲晢:Texas Instruments 瑷�(j矛)鏁�(sh霉)鍣ㄩ鍨�: 瑷�(j矛)鏁�(sh霉)闋嗗簭:Serial to Serial/Parallel 闆昏矾鏁�(sh霉)閲�:1 灏佽 / 绠遍珨:SOIC-20 Wide 閭忚集绯诲垪: 閭忚集椤炲瀷: 杓稿叆绶氳矾鏁�(sh霉)閲�:1 杓稿嚭椤炲瀷:Open Drain 鍌虫挱寤堕伈鏅�(sh铆)闁�:650 ns 鏈€澶у伐浣滄韩搴�:+ 125 C 鏈€灏忓伐浣滄韩搴�:- 40 C 灏佽:Reel |
| MC14094BDTR2G | 鍔熻兘鎻忚堪:瑷�(j矛)鏁�(sh霉)鍣ㄧЩ浣嶅瘎瀛樺櫒 3-18V 8-Bit Shift/Store RoHS:鍚� 鍒堕€犲晢:Texas Instruments 瑷�(j矛)鏁�(sh霉)鍣ㄩ鍨�: 瑷�(j矛)鏁�(sh霉)闋嗗簭:Serial to Serial/Parallel 闆昏矾鏁�(sh霉)閲�:1 灏佽 / 绠遍珨:SOIC-20 Wide 閭忚集绯诲垪: 閭忚集椤炲瀷: 杓稿叆绶氳矾鏁�(sh霉)閲�:1 杓稿嚭椤炲瀷:Open Drain 鍌虫挱寤堕伈鏅�(sh铆)闁�:650 ns 鏈€澶у伐浣滄韩搴�:+ 125 C 鏈€灏忓伐浣滄韩搴�:- 40 C 灏佽:Reel |
| MC14094BDTR2G-CUT TAPE | 鍒堕€犲晢:ON 鍔熻兘鎻忚堪:MC14094B Series 18 V 8-Stage Shift/Store Register w/Tri-State Output-TSSOP-16 |
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