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| 型號(hào)： | MC14082BDR2G |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類(lèi)： | 通用總線功能 |
| 英文描述： | B-SUFFIX SERIES CMOS GATES |
| 中文描述： | 4000/14000/40000 SERIES, DUAL 4-INPUT AND GATE, PDSO14 |
| 封裝： | LEAD FREE, SOIC-14 |
| 文件頁(yè)數(shù)： | 9/11頁(yè) |
| 文件大?。?/td> | 327K |
| 代理商： | MC14082BDR2G |
MOTOROLA CMOS LOGIC DATA
15
MC14001B
TYPICAL B–SERIES GATE CHARACTERISTICS (cont’d)
VOLTAGE TRANSFER CHARACTERISTICS
Figure 8. VDD = 5.0 Vdc
Figure 9. VDD = 10 Vdc
1.0
3.0
5.0
4.0
2.0
0
1.0
3.0
5.0
4.0
2.0
0
0
0
Vin, INPUT VOLTAGE (Vdc)
SINGLE INPUT NAND, AND
MULTIPLE INPUT NOR, OR
SINGLE INPUT NOR, OR
MULTIPLE INPUT NAND, AND
SINGLE INPUT NAND, AND
MULTIPLE INPUT NOR, OR
SINGLE INPUT NOR, OR
MULTIPLE INPUT NAND, AND
2.0
6.0
10
8.0
4.0
2.0
6.0
10
8.0
4.0
Vin, INPUT VOLTAGE (Vdc)
V
o
V
o
Figure 10. VDD = 15 Vdc
0
0
SINGLE INPUT NAND, AND
MULTIPLE INPUT NOR, OR
SINGLE INPUT NOR, OR
MULTIPLE INPUT NAND, AND
2.0
6.0
10
8.0
4.0
2.0
6.0
10
8.0
4.0
Vin, INPUT VOLTAGE (Vdc)
12
14
16
V
o
DC NOISE MARGIN
The DC noise margin is defined as the input voltage range
from an ideal “1” or “0” input level which does not produce
output state change(s). The typical and guaranteed limit val-
ues of the input values VIL and VIH for the output(s) to be at a
fixed voltage VO are given in the Electrical Characteristics
table. VIL and VIH are presented graphically in Figure 11.
Guaranteed minimum noise margins for both the “1” and
“0” levels =
1.0 V with a 5.0 V supply
2.0 V with a 10.0 V supply
2.5 V with a 15.0 V supply
Figure 11. DC Noise Immunity
Vout
VO
VO
VIL
0
VIH
Vin
VDD
VDD
Vout
VO
VO
VIL
0
VIH
Vin
VDD
VDD
(a) Inverting Function
(b) Non–Inverting Function
VSS = 0 VOLTS DC
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