
Semiconductor Components Industries, LLC, 2013
June, 2013 Rev. 7
1
Publication Order Number:
MC14076B/D
MC14076B
4-Bit D-Type Register
with Three-State Outputs
The MC14076B 4Bit Register consists of four Dtype flipflops
operating synchronously from a common clock. OR gated
outputdisable inputs force the outputs into a highimpedance state
for use in bus organized systems. OR gated datadisable inputs cause
the Q outputs to be fed back to the D inputs of the flipflops. Thus they
are inhibited from changing state while the clocking process remains
undisturbed. An asynchronous master root is provided to clear all four
flipflops simultaneously independent of the clock or disable inputs.
Features
ThreeState Outputs with Gated Control Lines
Fully Independent Clock Allows Unrestricted Operation for the Two
Modes: Parallel Load and Do Nothing
Asynchronous Master Reset
Four Bus Buffer Registers
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two LowPower TTL Loads or One LowPower
Schottky TTL Load Over the Rated Temperature Range
These are PbFree Devices*
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AECQ100
Qualified and PPAP Capable
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol
Parameter
Value
Unit
VDD
DC Supply Voltage Range
0.5 to +18.0
V
Vin, Vout
Input or Output Voltage Range
(DC or Transient)
0.5 to VDD + 0.5
V
Iin, Iout
Input or Output Current
(DC or Transient) per Pin
±10
mA
PD
Power Dissipation, per Package (Note
1)500
mW
TA
Ambient Temperature Range
55 to +125
°C
Tstg
Storage Temperature Range
65 to +150
°C
TL
Lead Temperature
(8Second Soldering)
260
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be
taken to avoid applications of any voltage higher than maximum rated voltages to this highimpedance circuit. For proper operation, Vin and Vout
should be constrained to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
*For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
MARKING
DIAGRAMS
PDIP16
P SUFFIX
CASE 648
MC14076BCP
AWLYYWWG
SOIC16
D SUFFIX
CASE 751B
14076BG
AWLYWW
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W = Work Week
G
= PbFree Package
See detailed ordering and shipping information in the package
dimensions section on page
3 of this data sheet.
ORDERING INFORMATION
16
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