參數(shù)資料
型號: MC14076B
廠商: ON SEMICONDUCTOR
英文描述: 4-Bit D-Type Register with Three-State Outputs
中文描述: 4位D類注冊的三態(tài)輸出
文件頁數(shù): 1/8頁
文件大?。?/td> 181K
代理商: MC14076B
Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 3
1
Publication Order Number:
MC14076B/D
The MC14076B 4–Bit Register consists of four D–type flip–flops
operating synchronously from a common clock. OR gated
output–disable inputs force the outputs into a high–impedance state
for use in bus organized systems. OR gated data–disable inputs cause
the Q outputs to be fed back to the D inputs of the flip–flops. Thus they
are inhibited from changing state while the clocking process remains
undisturbed. An asynchronous master root is provided to clear all four
flip–flops simultaneously independent of the clock or disable inputs.
Three–State Outputs with Gated Control Lines
Fully Independent Clock Allows Unrestricted Operation for the Two
Modes: Parallel Load and Do Nothing
Asynchronous Master Reset
Four Bus Buffer Registers
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low–Power TTL Loads or One Low–Power
Schottky TTL Load Over the Rated Temperature Range
MAXIMUM RATINGS
(Voltages Referenced to V
SS
) (Note 1.)
Symbol
Parameter
Value
Unit
V
DD
DC Supply Voltage Range
–0.5 to +18.0
V
V
in
, V
out
Input or Output Voltage Range
(DC or Transient)
–0.5 to V
DD
+ 0.5
V
I
in
, I
out
Input or Output Current
(DC or Transient) per Pin
±
10
mA
P
D
Power Dissipation,
per Package (Note 2.)
500
mW
T
A
Ambient Temperature Range
–55 to +125
°
C
T
stg
Storage Temperature Range
–65 to +150
°
C
T
L
Lead Temperature
(8–Second Soldering)
260
°
C
1. Maximum Ratings are those values beyond which damage to the device
may occur.
2. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
(V
in
or V
out
)
V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V
SS
or V
DD
). Unused outputs must be left open.
http://onsemi.com
A
WL or L
YY or Y
WW or W = Work Week
= Assembly Location
= Wafer Lot
= Year
Device
Package
Shipping
ORDERING INFORMATION
MC14076BCP
PDIP–16
2000/Box
MC14076BD
SOIC–16
2400/Box
MC14076BDR2
SOIC–16
2500/Tape & Reel
MARKING
DIAGRAMS
16
1
PDIP–16
P SUFFIX
CASE 648
MC14076BCP
AWLYYWW
SOIC–16
D SUFFIX
CASE 751B
1
16
14076B
AWLYWW
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