
MOTOROLA CMOS LOGIC DATA
3
MC14060B
Characteristic
Output Rise Time (Counter Outputs)
Symbol
Vdc
5.0
10
Min
—
—
Typ #
40
25
Max
200
100
Unit
ns
10
15
—
—
30
20
100
80
Propagation Delay Time
tPLH
5.0
15
—
—
415
125
740
200
ns
Clock to Q14
5.0
—
1.5
2.7
μ
s
10
40
30
—
φ
15
—
17
12
Clock Rise and Fall Time
tTLH
tTHL
5.0
10
ns
10
60
Propagation Delay Time
tPHL
5.0
15
—
—
15
170
60
—
—
350
100
ns
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
Figure 1. Power Dissipation Test Circuit
and Waveform
Figure 2. Switching Time Test Circuit
and Waveforms
PULSE
GENERATOR
ID
VDD
500
μ
F
0.01
μ
F
CLOCK
NC
NC
Q4
Q5
Qn
R
OUT1
OUT2
VSS
CL
CL
CL
20 ns
20 ns
CLOCK
90%
50%
10%
50% DUTY CYCLE
VDD
VSS
PULSE
GENERATOR
VDD
CLOCK
NC
NC
Q4
Q5
Qn
R
OUT1
OUT2
VSS
CL
CL
CL
20 ns
20 ns
CLOCK
Q
tTLH
tTHL
tPLH
tPHL
tWH
90%
50%
10%
90%
50%
10%