Semiconductor Components Industries, LLC, 2005
February, 2005 Rev. 5
1
Publication Order Number:
MC14049B/D
MC14049B, MC14050B
Hex Buffer
The MC14049B Hex Inverter/Buffer and MC14050B Noninverting
Hex Buffer are constructed with MOS PChannel and NChannel
enhancement mode devices in a single monolithic structure. These
complementary MOS devices find primary use where low power
dissipation and/or high noise immunity is desired. These devices
provide logic level conversion using only one supply voltage, V
DD
.
The inputsignal high level (V
IH
) can exceed the V
DD
supply
voltage for logic level conversions. Two TTL/DTL loads can be driven
when the devices are used as a CMOStoTTL/DTL converter
(V
DD
= 5.0 V, V
OL
0.4 V,
I
OL
≥
3.2 mA).
Note that pins 13 and 16 are not connected internally on these
devices; consequently connections to these terminals will not affect
circuit operation.
Features
High Source and Sink Currents
HightoLow Level Converter
Supply Voltage Range = 3.0 V to 18 V
V
IN
can exceed V
DD
Meets JEDEC B Specifications
Improved ESD Protection On All Inputs
PbFree Packages are Available*
MAXIMUM RATINGS
(Voltages Referenced to V
SS
)
Symbol
Parameter
Value
Unit
V
DD
V
in
V
out
DC Supply Voltage Range
0.5 to +18.0
V
Input Voltage Range (DC or Transient)
0.5 to +18.0
V
Output Voltage Range (DC or Transient)
0.5 to V
DD
+
0.5
V
I
in
I
out
P
D
Input Current (DC or Transient) per Pin
±
10
±
45
mA
Output Current (DC or Transient) per Pin
mA
Power Dissipation, per Package (Note 1)
(Plastic)
(SOIC)
825
740
mW
T
A
T
stg
T
L
Ambient Temperature Range
55 to +125
°
C
°
C
°
C
Storage Temperature Range
65 to +150
Lead Temperature (8Second Soldering)
260
1. Temperature Derating: See Figure 3.
This device contains protection circuitry to protect the inputs against damage
due to high static voltages or electric fields referenced to the V
SS
pin only. Extra
precautions must be taken to avoid applications of any voltage higher than the
maximum rated voltages to this highimpedance circuit. For proper operation, the
ranges V
SS
≤
V
in
≤
18 V and V
SS
≤
V
out
≤
V
DD
are recommended.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V
SS
or V
DD
). Unused outputs must be left open.
*For additional information on our PbFree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
http://onsemi.com
MARKING
DIAGRAMS
PDIP16
P SUFFIX
CASE 648
MC140xxBCP
AWLYYWW
SOIC16
D SUFFIX
CASE 751B
TSSOP16
DT SUFFIX
CASE 948F
140xxB
AWLYWW
14
0xxB
ALYW
xx
A
WL, L
YY, Y
WW, W
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
SOEIAJ16
F SUFFIX
CASE 966
MC140xxB
AWLYWW
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
ORDERING INFORMATION
16
1
1
16
1
16
1
16