MOTOROLA CMOS LOGIC DATA
MC14035B
144
The MC14035B 4–bit shift register is constructed with MOS P–channel
and N–channel enhancement mode devices in a single monolithic structure.
It consists of a 4–stage clocked serial–shift register with synchronous
parallel inputs and buffered parallel outputs. The Parallel/Serial (P/S) input
allows serial–right shifting of data or synchronous parallel loading via inputs
DP0 thru DP3. The True/Complement (T/C) input determines whether the
outputs display the Q or Q outputs of the flip–flop stages. J–K logic forms the
serial input to the first stage. With the J and K inputs connected together they
operate as a serial “D” input.
This device may be effectively used for shift–right/shift–left registers,
parallel–to–serial/serial–to–parallel conversion, sequence generation, up/
down Johnson or ring counters, pseudo–random code generation, frequen-
cy and phase comparators, sample and hold registers, etc . . .
4–Stage Clocked Serial–Shift Operation
Synchronous Parallel Loading of all Four Stages
J–K Serial Inputs on First Stage
Asynchronous True/Complement Control of all Outputs
Fully Static Operation
Asynchronous Master Reset
Data Transfer Occurs on the Positive–Going Clock Transition
No Limit on Clock Rise and Fall Times
All Inputs are Buffered
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Schottky TTL Load Over the Rated Temperature Range
MAXIMUM RATINGS*
(Voltages Referenced to VSS)
Symbol
Parameter
VDD
DC Supply Voltage
Vin, Vout
Input or Output Voltage (DC or Transient)
lin, lout
Input or Output Current (DC or Transient),
Value
– 0.5 to + 18.0
– 0.5 to VDD + 0.5
±
10
Unit
V
V
mA
Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C
TRUTH TABLE
Inputs
C
J
K
R
Q0
0
tn Output
0
0
1
0
1
0
0
0
0
Q0 (n – 1)
Q0 (n – 1)
1
X
X
1
X
X
0
0
1
1
Q0 (n – 1)
0
X
X = Don’t Care
P/S = 0 = Serial Mode
T/C = 1 = True Outputs
SEMICONDUCTOR TECHNICAL DATA
REV 3
1/94
L SUFFIX
CERAMIC
CASE 620
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
TA = – 55
°
to 125
°
C for all packages.
Plastic
Ceramic
SOIC
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
PIN ASSIGNMENT
13
14
15
16
9
10
11
12
5
4
3
2
1
8
7
6
DP3
Q3
Q2
Q1
VDD
DP0
DP1
DP2
J
K
T/C
Q0
VSS
P/S
C
R