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參數(shù)資料
| 型號(hào)： | MC14027BFL1 |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類(lèi)： | 鎖存器 |
| 英文描述： | 4000/14000/40000 SERIES, DUAL POSITIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16 |
| 封裝： | EIAJ, PLASTIC, SOIC-16 |
| 文件頁(yè)數(shù)： | 4/10頁(yè) |
| 文件大?。?/td> | 205K |
| 代理商： | MC14027BFL1 |
MC14027B
http://onsemi.com
3
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
VDD
– 55
_C
25
_C
125
_C
Characteristic
Symbol
VDD
Vdc
Min
Max
Min
Typ (4.)
Max
Min
Max
Unit
Output Voltage
“0” Level
Vin = VDD or 0
VOL
5.0
10
15
—
0.05
—
0
0.05
—
0.05
Vdc
Vin = 0 or VDD
“1” Level
VOH
5.0
10
15
4.95
9.95
14.95
—
4.95
9.95
14.95
5.0
10
15
—
4.95
9.95
14.95
—
Vdc
Input Voltage
“0” Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
5.0
10
15
—
1.5
3.0
4.0
—
2.25
4.50
6.75
1.5
3.0
4.0
—
1.5
3.0
4.0
Vdc
(VO = 0.5 or 4.5 Vdc)
“1” Level
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
VIH
5.0
10
15
3.5
7.0
11
—
3.5
7.0
11
2.75
5.50
8.25
—
3.5
7.0
11
—
Vdc
Output Drive Current
(VOH = 2.5 Vdc)
Source
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
IOH
5.0
10
15
– 3.0
– 0.64
– 1.6
– 4.2
—
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
—
– 1.7
– 0.36
– 0.9
– 2.4
—
mAdc
(VOL = 0.4 Vdc)
Sink
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
IOL
5.0
10
15
0.64
1.6
4.2
—
0.51
1.3
3.4
0.88
2.25
8.8
—
0.36
0.9
2.4
—
mAdc
Input Current
Iin
15
—
± 0.1
—
±0.00001
± 0.1
—
± 1.0
Adc
Input Capacitance
(Vin = 0)
Cin
—
—
—
—
5.0
7.5
—
—
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
—
1.0
2.0
4.0
—
0.002
0.004
0.006
1.0
2.0
4.0
—
30
60
120
Adc
Total Supply Current (5.) (6.)
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)
IT
5.0
10
15
IT = (0.8 A/kHz) f + IDD
IT = (1.6 A/kHz) f + IDD
IT = (2.4 A/kHz) f + IDD
Adc
4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
5. The formulas given are for the typical characteristics only at 25
_C.
6. To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in A (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.002.
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