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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | MC14023BDR2 |
| 寤犲晢锛� | ON Semiconductor |
| 鏂囦欢闋佹暩(sh霉)锛� | 10/12闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC GATE NAND TRIPLE CMOS 14SOIC |
| 鐢�(ch菐n)鍝佽畩鍖栭€氬憡锛� | Product Discontinuation 27/Jan/2012 |
| 妯欐簴鍖呰锛� | 1 |
| 绯诲垪锛� | 4000B |
| 閭忚集椤炲瀷锛� | 鑸囬潪闁€ |
| 闆昏矾鏁�(sh霉)锛� | 3 |
| 杓稿叆鏁�(sh霉)锛� | 3 |
| 闆绘簮闆诲锛� | 3 V ~ 18 V |
| 闆绘祦 - 闈滄厠(t脿i)锛堟渶澶у€硷級锛� | 1µA |
| 杓稿嚭闆绘祦楂�锛屼綆锛� | 8.8mA锛�8.8mA |
| 閭忚集闆诲钩 - 浣庯細 | 1.5 V ~ 4 V |
| 閭忚集闆诲钩 - 楂橈細 | 3.5 V ~ 11 V |
| 椤嶅畾闆诲鍜屾渶澶� CL 鏅傜殑鏈€澶у偝鎾欢閬诧細 | 100ns @ 15V锛�50pF |
| 宸ヤ綔婧害锛� | -55°C ~ 125°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 14-SOICN |
| 灏佽/澶栨锛� | 14-SOIC锛�0.154"锛�3.90mm 瀵級 |
| 鍖呰锛� | 妯欐簴鍖呰 |
| 鍏跺畠鍚嶇ū锛� | MC14023BDR2OSDKR |
MC14001B Series
http://onsemi.com
7
TYPICAL BSERIES GATE CHARACTERISTICS (cont鈥檇)
VOLTAGE TRANSFER CHARACTERISTICS
Figure 8. VDD = 5.0 Vdc
Figure 9. VDD = 10 Vdc
1.0
3.0
5.0
4.0
2.0
0
1.0
3.0
5.0
4.0
2.0
0
Vin, INPUT VOLTAGE (Vdc)
SINGLE INPUT NAND, AND
MULTIPLE INPUT NOR, OR
SINGLE INPUT NOR, OR
MULTIPLE INPUT NAND, AND
SINGLE INPUT NAND, AND
MULTIPLE INPUT NOR, OR
SINGLE INPUT NOR, OR
MULTIPLE INPUT NAND, AND
2.0
6.0
10
8.0
4.0
2.0
6.0
10
8.0
4.0
Vin, INPUT VOLTAGE (Vdc)
V
,
out
OUTPUT
VOL
TAGE
(Vdc)
V
,
out
OUTPUT
VOL
TAGE
(Vdc)
Figure 10. VDD = 15 Vdc
0
SINGLE INPUT NAND, AND
MULTIPLE INPUT NOR, OR
SINGLE INPUT NOR, OR
MULTIPLE INPUT NAND, AND
2.0
6.0
10
8.0
4.0
2.0
6.0
10
8.0
4.0
Vin, INPUT VOLTAGE (Vdc)
12
14
16
V
,
out
OUTPUT
VOL
TAGE
(Vdc)
DC NOISE MARGIN
The DC noise margin is defined as the input voltage range
from an ideal 鈥�1鈥� or 鈥�0鈥� input level which does not produce
output state change(s). The typical and guaranteed limit
values of the input values VIL and VIH for the output(s) to
be at a fixed voltage VO are given in the Electrical
Characteristics table. VIL and VIH are presented graphically
in Figure 11.
Guaranteed minimum noise margins for both the 鈥�1鈥� and
鈥�0鈥� levels =
1.0 V with a 5.0 V supply
2.0 V with a 10.0 V supply
2.5 V with a 15.0 V supply
Figure 11. DC Noise Immunity
Vout
VO
VIL
0
VIH
Vin
VDD
Vout
VO
VIL
0
VIH
Vin
VDD
(a) Inverting Function
(b) NonInverting Function
VSS = 0 VOLTS DC
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| MC74AC14N | IC SCHMITT TRIGGER HEX INV 14DIP |
| MC100EL32DT | IC DIVIDER DIV X2 ECL 5V 8TSSOP |
| OSTTS14015A | CONN TERM BLK PLUG 14POS 7.62MM |
| OSTVD173150 | TERM BLOCK PLUG 3.81MM 17POS |
| OSTTS15715D | TERM BLOCK PLUG 5.0MM 15POS |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| MC14023BDR2G | 鍔熻兘鎻忚堪:閭忚集闁€ 3-18V Triple 3-Input NAND RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鐢�(ch菐n)鍝�:OR 閭忚集绯诲垪:LVC 鏌垫サ鏁�(sh霉)閲�:2 绶氳矾鏁�(sh霉)閲忥紙杓稿叆/杓稿嚭锛�:2 / 1 楂橀浕骞宠几鍑洪浕娴�:- 16 mA 浣庨浕骞宠几鍑洪浕娴�:16 mA 鍌虫挱寤堕伈鏅傞枔:3.8 ns 闆绘簮闆诲-鏈€澶�:5.5 V 闆绘簮闆诲-鏈€灏�:1.65 V 鏈€澶у伐浣滄韩搴�:+ 125 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:DCU-8 灏佽:Reel |
| MC14023BF | 鍒堕€犲晢:Rochester Electronics LLC 鍔熻兘鎻忚堪:- Bulk |
| MC14023BFEL | 鍔熻兘鎻忚堪:閭忚集闁€ 3-18V Triple 3-Input RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鐢�(ch菐n)鍝�:OR 閭忚集绯诲垪:LVC 鏌垫サ鏁�(sh霉)閲�:2 绶氳矾鏁�(sh霉)閲忥紙杓稿叆/杓稿嚭锛�:2 / 1 楂橀浕骞宠几鍑洪浕娴�:- 16 mA 浣庨浕骞宠几鍑洪浕娴�:16 mA 鍌虫挱寤堕伈鏅傞枔:3.8 ns 闆绘簮闆诲-鏈€澶�:5.5 V 闆绘簮闆诲-鏈€灏�:1.65 V 鏈€澶у伐浣滄韩搴�:+ 125 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:DCU-8 灏佽:Reel |
| MC14023BFELG | 鍔熻兘鎻忚堪:閭忚集闁€ 3-18V Triple 3-Input NAND RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鐢�(ch菐n)鍝�:OR 閭忚集绯诲垪:LVC 鏌垫サ鏁�(sh霉)閲�:2 绶氳矾鏁�(sh霉)閲忥紙杓稿叆/杓稿嚭锛�:2 / 1 楂橀浕骞宠几鍑洪浕娴�:- 16 mA 浣庨浕骞宠几鍑洪浕娴�:16 mA 鍌虫挱寤堕伈鏅傞枔:3.8 ns 闆绘簮闆诲-鏈€澶�:5.5 V 闆绘簮闆诲-鏈€灏�:1.65 V 鏈€澶у伐浣滄韩搴�:+ 125 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:DCU-8 灏佽:Reel |
| MC14023BFL1 | 鍒堕€犲晢:Rochester Electronics LLC 鍔熻兘鎻忚堪:- Bulk |
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