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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | MC14018BCP |
| 寤犲晢锛� | ON Semiconductor |
| 鏂囦欢闋佹暩(sh霉)锛� | 4/7闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC COUNTER N PRESET 16-DIP |
| 鐢�(ch菐n)鍝佽畩鍖栭€氬憡锛� | Product Discontinuation 20/Aug/2008 |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 25 |
| 绯诲垪锛� | 4000B |
| 閭忚集椤炲瀷锛� | 闄や互 N |
| 鍏冧欢鏁�(sh霉)锛� | 1 |
| 姣忓€�(g猫)鍏冧欢鐨勪綅鍏冩暩(sh霉)锛� | 5 |
| 寰�(f霉)浣嶏細 | 鐣版 |
| 瑷�(j矛)鏅�(sh铆)锛� | 鍚屾 |
| 瑷�(j矛)鏁�(sh霉)閫熺巼锛� | 8MHz |
| 瑙哥櫦(f膩)鍣ㄩ鍨嬶細 | 姝ｉ倞娌� |
| 闆绘簮闆诲锛� | 3 V ~ 18 V |
| 宸ヤ綔婧害锛� | -55°C ~ 125°C |
| 瀹夎椤炲瀷锛� | 閫氬瓟 |
| 灏佽/澶栨锛� | 16-DIP锛�0.300"锛�7.62mm锛� |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 16-DIP |
| 鍖呰锛� | 绠′欢 |
MC14018B
http://onsemi.com
4
Characteristic
Symbol
VDD
Vdc
All Types
Unit
Min
Typ
(Note 6)
Max
Output Rise and Fall Time
tTLH, tTHL = (1.35 ns/pF) CL + 32 ns
tTLH, tTHL = (0.6 ns/pF) CL + 20 ns
tTLH, tTHL = (0.4 ns/pF) CL + 20 ns
tTLH, tTHL
5.0
10
15
鈥�
100
50
40
200
100
80
ns
Propagation Delay Time
Clock to Q
tPLH, tPHL = (0.90 ns/pF) CL + 265 ns
tPLH, tPHL = (0.36 ns/pF) CL + 102 ns
tPLH, tPHL = (0.26 ns/pF) CL + 72 ns
tPLH,
tPHL
5.0
10
15
鈥�
310
120
85
620
240
170
ns
Reset to Q
tPLH = (0.90 ns/pF) CL + 325 ns
tPLH = (0.36 ns/pF) CL + 132 ns
tPLH = (0.26 ns/pF) CL + 81 ns
5.0
10
15
鈥�
370
150
100
740
300
200
ns
Preset Enable to Q
tPLH, tPHL = (0.90 ns/pF) CL + 325 ns
tPLH, tPHL = (0.36 ns/pF) CL + 132 ns
tPLH, tPHL = (0.26 ns/pF) CL + 81 ns
5.0
10
15
鈥�
370
150
100
740
300
200
ns
Setup Time
Data (Pin 1) to Clock
tsu
5.0
10
15
200
100
80
0
鈥�
ns
Jam Inputs to Preset Enable
5.0
10
15
200
100
80
0
鈥�
ns
Data (Jam Inputs)toPreset
Enable Hold Time
th
5.0
10
15
540
500
480
270
250
240
鈥�
ns
Clock Pulse Width
tWH
5.0
10
15
400
200
160
200
100
80
鈥�
ns
Reset or Preset Enable
Pulse Width
tWH
5.0
10
15
290
130
110
145
65
55
鈥�
ns
Clock Rise and Fall Time
tTLH, tTHL
5.0
10
15
No Limit
ns
Clock Pulse Frequency
fcl
5.0
10
15
鈥�
2.5
6.5
8.0
1.25
3.25
4.0
MHz
5. The formulas given are for the typical characteristics only at 25_C.
6. Data labelled 鈥淭yp鈥� is not to be used for design purposes but is intended as an indication of the IC鈥檚 potential performance.
Figure 1. Switching Time Waveforms
ANY INPUT
ANY OUTPUT
20 ns
90%
50%
10%
VDD
VSS
VOH
VOL
tPLH
tPHL
tTLH
tTHL
90%
50%
10%
鐩搁棞(gu膩n)PDF璩囨枡 |
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| MC14018BCPG | 鍔熻兘鎻忚堪:瑷�(j矛)鏁�(sh霉)鍣ㄧЩ浣嶅瘎瀛樺櫒 LOG CMOS COUNTER DIVIDE RoHS:鍚� 鍒堕€犲晢:Texas Instruments 瑷�(j矛)鏁�(sh霉)鍣ㄩ鍨�: 瑷�(j矛)鏁�(sh霉)闋嗗簭:Serial to Serial/Parallel 闆昏矾鏁�(sh霉)閲�:1 灏佽 / 绠遍珨:SOIC-20 Wide 閭忚集绯诲垪: 閭忚集椤炲瀷: 杓稿叆绶氳矾鏁�(sh霉)閲�:1 杓稿嚭椤炲瀷:Open Drain 鍌虫挱寤堕伈鏅�(sh铆)闁�:650 ns 鏈€澶у伐浣滄韩搴�:+ 125 C 鏈€灏忓伐浣滄韩搴�:- 40 C 灏佽:Reel |
| MC14018BD | 鍔熻兘鎻忚堪:瑷�(j矛)鏁�(sh霉)鍣ㄧЩ浣嶅瘎瀛樺櫒 LOG CMOS COUNTER DIVIDE RoHS:鍚� 鍒堕€犲晢:Texas Instruments 瑷�(j矛)鏁�(sh霉)鍣ㄩ鍨�: 瑷�(j矛)鏁�(sh霉)闋嗗簭:Serial to Serial/Parallel 闆昏矾鏁�(sh霉)閲�:1 灏佽 / 绠遍珨:SOIC-20 Wide 閭忚集绯诲垪: 閭忚集椤炲瀷: 杓稿叆绶氳矾鏁�(sh霉)閲�:1 杓稿嚭椤炲瀷:Open Drain 鍌虫挱寤堕伈鏅�(sh铆)闁�:650 ns 鏈€澶у伐浣滄韩搴�:+ 125 C 鏈€灏忓伐浣滄韩搴�:- 40 C 灏佽:Reel |
| MC14018BDG | 鍔熻兘鎻忚堪:瑷�(j矛)鏁�(sh霉)鍣ㄧЩ浣嶅瘎瀛樺櫒 LOG CMOS COUNTER DIVIDE RoHS:鍚� 鍒堕€犲晢:Texas Instruments 瑷�(j矛)鏁�(sh霉)鍣ㄩ鍨�: 瑷�(j矛)鏁�(sh霉)闋嗗簭:Serial to Serial/Parallel 闆昏矾鏁�(sh霉)閲�:1 灏佽 / 绠遍珨:SOIC-20 Wide 閭忚集绯诲垪: 閭忚集椤炲瀷: 杓稿叆绶氳矾鏁�(sh霉)閲�:1 杓稿嚭椤炲瀷:Open Drain 鍌虫挱寤堕伈鏅�(sh铆)闁�:650 ns 鏈€澶у伐浣滄韩搴�:+ 125 C 鏈€灏忓伐浣滄韩搴�:- 40 C 灏佽:Reel |
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