
Semiconductor Components Industries, LLC, 2005
August, 2005 Rev. 6
1
Publication Order Number:
MC14015B/D
MC14015B
Dual 4Bit Static
Shift Register
The MC14015B dual 4bit static shift register is constructed with
MOS PChannel and NChannel enhancement mode devices in a
single monolithic structure. It consists of two identical, independent
4state serialinput/paralleloutput registers. Each register has
independent Clock and Reset inputs with a single serial Data input.
The register states are type D masterslave flipflops. Data is shifted
from one stage to the next during the positivegoing clock transition.
Each register can be cleared when a high level is applied on the Reset
line. These complementary MOS shift registers find primary use in
buffer storage and serialtoparallel conversion where low power
dissipation and/or noise immunity is desired.
Features
Diode Protection on All Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Logic EdgeClocked FlipFlop Design
Logic state is retained indefinitely with clock level either high or
low; information is transferred to the output only on the positive
going edge of the clock pulse
Capable of Driving Two Lowpower TTL Loads or One Lowpower
Schottky TTL Load Over the Rated Temperature Range
PbFree Packages are Available*
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol
Parameter
Value
Unit
VDD
DC Supply Voltage Range
0.5 to +18.0
V
Vin, Vout
Input or Output Voltage Range
(DC or Transient)
0.5 to VDD + 0.5
V
Iin, Iout
Input or Output Current
(DC or Transient) per Pin
±10
mA
PD
Power Dissipation, per Package
500
mW
TA
Ambient Temperature Range
55 to +125
°C
Tstg
Storage Temperature Range
65 to +150
°C
TL
Lead Temperature
(8Second Soldering)
260
°C
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/
_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
highimpedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
http://onsemi.com
MARKING
DIAGRAMS
PDIP16
P SUFFIX
CASE 648
MC14015BCP
AWLYYWWG
SOIC16
D SUFFIX
CASE 751B
TSSOP16
DT SUFFIX
CASE 948F
14015BG
AWLYWW
14
015B
ALYW
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W
= Work Week
G
= PbFree Indicator
SOEIAJ16
F SUFFIX
CASE 966
MC14015B
ALYWG
See detailed ordering and shipping information in the package
ORDERING INFORMATION
16
1
16
1
16
1
16
*For additional information on our PbFree strategy
and soldering details, please download the
ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.