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參數(shù)資料
| 型號： | MC14013BFR1 |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 鎖存器 |
| 英文描述： | 4000/14000/40000 SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14 |
| 封裝： | EIAJ, SO-14 |
| 文件頁數(shù)： | 4/9頁 |
| 文件大?。?/td> | 162K |
| 代理商： | MC14013BFR1 |
MC14013B
http://onsemi.com
4
Characteristic
Symbol
VDD
Min
Typ (6)
Max
Unit
Output Rise and Fall Time
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns
tTLH,
tTHL
5.0
10
15
100
50
40
200
100
80
ns
Propagation Delay Time
Clock to Q, Q
tPLH, tPHL = (1.7 ns/pF) CL + 90 ns
tPLH, tPHL = (0.66 ns/pF) CL + 42 ns
tPLH, tPHL = (0.5 ns/pF) CL + 25 ns
tPLH
tPHL
5.0
10
15
175
75
50
350
150
100
ns
Set to Q, Q
tPLH, tPHL = (1.7 ns/pF) CL + 90 ns
tPLH, tPHL = (0.66 ns/pF) CL + 42 ns
tPLH, tPHL = (0.5 ns/pF) CL + 25 ns
5.0
10
15
175
75
50
350
150
100
Reset to Q, Q
tPLH, tPHL = (1.7 ns/pF) CL + 265 ns
tPLH, tPHL = (0.66 ns/pF) CL + 67 ns
tPLH, tPHL = (0.5 ns/pF) CL + 50 ns
5.0
10
15
225
100
75
450
200
150
Setup Times (7)
tsu
5.0
10
15
40
20
15
20
10
7.5
ns
Hold Times (7)
th
5.0
10
15
40
20
15
20
10
7.5
ns
Clock Pulse Width
tWL, tWH
5.0
10
15
250
100
70
125
50
35
ns
Clock Pulse Frequency
fcl
5.0
10
15
4.0
10
14
2.0
5.0
7.0
MHz
Clock Pulse Rise and Fall Time
tTLH
tTHL
5.0
10
15
15
5.0
4.0
ms
Set and Reset Pulse Width
tWL, tWH
5.0
10
15
250
100
70
125
50
35
ns
Removal Times
Set
trem
5
10
15
80
45
35
0
5
ns
Reset
5
10
15
50
30
25
– 35
– 10
– 5
5. The formulas given are for the typical characteristics only at 25_C.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
7. Data must be valid for 250 ns with a 5 V supply, 100 ns with 10 V, and 70 ns with 15 V.
LOGIC DIAGRAM (1/2 of Device Shown)
R
C
D
S
C
CC
C
Q
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