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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | MC14013BCPG |
| 寤犲晢锛� | ON Semiconductor |
| 鏂囦欢闋佹暩(sh霉)锛� | 4/9闋� |
| 鏂囦欢澶у皬锛� | 0K |
| 鎻忚堪锛� | IC FLIP FLOP DUAL TYPE D 14DIP |
| 妯欐簴鍖呰锛� | 500 |
| 绯诲垪锛� | 4000B |
| 鍔熻兘锛� | 瑷�(sh猫)缃紙闋愯ō(sh猫)锛夊拰寰╀綅 |
| 椤炲瀷锛� | D 鍨� |
| 杓稿嚭椤炲瀷锛� | 宸垎 |
| 鍏冧欢鏁�(sh霉)锛� | 2 |
| 姣忓€嬪厓浠剁殑浣嶅厓鏁�(sh霉)锛� | 1 |
| 闋荤巼 - 鏅傞悩锛� | 14MHz |
| 寤堕伈鏅傞枔 - 鍌宠几锛� | 50ns |
| 瑙哥櫦(f膩)鍣ㄩ鍨嬶細 | 姝ｉ倞娌� |
| 杓稿嚭闆绘祦楂橈紝浣庯細 | 8.8mA锛�8.8mA |
| 闆绘簮闆诲锛� | 3 V ~ 18 V |
| 宸ヤ綔婧害锛� | -55°C ~ 125°C |
| 瀹夎椤炲瀷锛� | 閫氬瓟 |
| 灏佽/澶栨锛� | 14-DIP锛�0.300"锛�7.62mm锛� |
| 鍖呰锛� | 绠′欢 |
| 鐢�(ch菐n)鍝佺洰閷勯爜闈細 | 1124 (CN2011-ZH PDF) |
| 鍏跺畠鍚嶇ū锛� | MC14013BCPGOS |
MC14013B
http://onsemi.com
4
Characteristic
Symbol
VDD
Min
Typ (6)
Max
Unit
Output Rise and Fall Time
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns
tTLH,
tTHL
5.0
10
15
100
50
40
200
100
80
ns
Propagation Delay Time
Clock to Q, Q
tPLH, tPHL = (1.7 ns/pF) CL + 90 ns
tPLH, tPHL = (0.66 ns/pF) CL + 42 ns
tPLH, tPHL = (0.5 ns/pF) CL + 25 ns
tPLH
tPHL
5.0
10
15
175
75
50
350
150
100
ns
Set to Q, Q
tPLH, tPHL = (1.7 ns/pF) CL + 90 ns
tPLH, tPHL = (0.66 ns/pF) CL + 42 ns
tPLH, tPHL = (0.5 ns/pF) CL + 25 ns
5.0
10
15
175
75
50
350
150
100
Reset to Q, Q
tPLH, tPHL = (1.7 ns/pF) CL + 265 ns
tPLH, tPHL = (0.66 ns/pF) CL + 67 ns
tPLH, tPHL = (0.5 ns/pF) CL + 50 ns
5.0
10
15
225
100
75
450
200
150
Setup Times (7)
tsu
5.0
10
15
40
20
15
20
10
7.5
ns
Hold Times (7)
th
5.0
10
15
40
20
15
20
10
7.5
ns
Clock Pulse Width
tWL, tWH
5.0
10
15
250
100
70
125
50
35
ns
Clock Pulse Frequency
fcl
5.0
10
15
4.0
10
14
2.0
5.0
7.0
MHz
Clock Pulse Rise and Fall Time
tTLH
tTHL
5.0
10
15
15
5.0
4.0
ms
Set and Reset Pulse Width
tWL, tWH
5.0
10
15
250
100
70
125
50
35
ns
Removal Times
Set
trem
5
10
15
80
45
35
0
5
ns
Reset
5
10
15
50
30
25
鈥� 35
鈥� 10
鈥� 5
5. The formulas given are for the typical characteristics only at 25_C.
6. Data labelled 鈥淭yp鈥� is not to be used for design purposes but is intended as an indication of the IC鈥檚 potential performance.
7. Data must be valid for 250 ns with a 5 V supply, 100 ns with 10 V, and 70 ns with 15 V.
LOGIC DIAGRAM (1/2 of Device Shown)
R
C
D
S
C
CC
C
Q
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| MC14013BDR2 | 鍔熻兘鎻忚堪:瑙哥櫦(f膩)鍣� 3-18V CMOS Dual RoHS:鍚� 鍒堕€犲晢:Texas Instruments 闆昏矾鏁�(sh霉)閲�:2 閭忚集绯诲垪:SN74 閭忚集椤炲瀷:D-Type Flip-Flop 妤垫€�:Inverting, Non-Inverting 杓稿叆椤炲瀷:CMOS 杓稿嚭椤炲瀷: 鍌虫挱寤堕伈鏅傞枔:4.4 ns 楂橀浕骞宠几鍑洪浕娴�:- 16 mA 浣庨浕骞宠几鍑洪浕娴�:16 mA 闆绘簮闆诲-鏈€澶�:5.5 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:X2SON-8 灏佽:Reel |
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