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參數(shù)資料
| 型號： | MC14001UBDR2G |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 3/7頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC GATE NOR QUAD 2INPUT 14-SOIC |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | 4000B |
| 邏輯類型： | 或非門 |
| 電路數(shù)： | 4 |
| 輸入數(shù)： | 2 |
| 電源電壓： | 3 V ~ 18 V |
| 電流 - 靜態(tài)（最大值）： | 1µA |
| 輸出電流高，低： | 3.5mA，8.8mA |
| 邏輯電平 - 低： | 1 V ~ 2.5 V |
| 邏輯電平 - 高： | 4 V ~ 12.5 V |
| 額定電壓和最大 CL 時的最大傳播延遲： | 80ns @ 15V，50pF |
| 工作溫度： | -55°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 供應(yīng)商設(shè)備封裝： | 14-SOICN |
| 封裝/外殼： | 14-SOIC（0.154"，3.90mm 寬） |
| 包裝： | 帶卷 (TR) |
MC14001UB, MC14011UB
http://onsemi.com
3
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic
Symbol
VDD
Vdc
55_C
25_C
125_C
Unit
Min
Max
Min
Typ
(Note 2)
Max
Min
Max
Output Voltage
“0” Level
Vin = VDD or 0
VOL
5.0
10
15
0.05
0
0.05
0.05
Vdc
Vin = 0 or VDD
“1” Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
Input Voltage
“0” Level
(VO = 4.5 Vdc)
(VO = 9.0 Vdc)
(VO = 13.5 Vdc)
VIL
5.0
10
15
1.0
2.0
2.5
2.25
4.50
6.75
1.0
2.0
2.5
1.0
2.0
2.5
Vdc
(VO = 0.5 Vdc)
“1” Level
(VO = 1.0 Vdc)
(VO = 1.5 Vdc)
VIH
5.0
10
15
4.0
8.0
12.5
4.0
8.0
12.5
2.75
5.50
8.25
4.0
8.0
12.5
Vdc
Output Drive Current
(VOH = 2.5 Vdc)
Source
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
IOH
5.0
10
15
– 1.0
– 0.25
– 0.62
– 1.8
– 0.75
– 0.2
– 0.4
– 1.5
– 1.7
– 0.36
– 0.9
– 3.5
– 0.55
– 0.14
– 0.15
– 1.0
mAdc
(VOL = 0.4 Vdc)
Sink
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.1
3.4
0.88
2.25
8.8
0.36
0.7
2.4
mAdc
Input Current
Iin
15
± 0.1
±0.00001
± 0.1
± 1.0
mAdc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
0.25
0.5
1.0
0.0005
0.0010
0.0015
0.25
0.5
1.0
7.5
15
30
mAdc
Total Supply Current (Notes 3, 4)
(Dynamic plus Quiescent,
Per Gate CL = 50 pF)
IT
5.0
10
15
IT = (0.3 mA/kHz) f + IDD/N
IT = (0.6 mA/kHz) f + IDD/N
IT = (0.8 mA/kHz) f + IDD/N
mAdc
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25_C.
4. To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL 50) Vfk
where: IT is in mH (per package), CL in pF, V = (VDD VSS) in volts, f in kHz is input frequency, and k = 0.001 x the number of exercised gates
per package.
Characteristic
Symbol
VDD
Vdc
Min
Typ
(Note 6)
Max
Unit
Output Rise Time
tTLH = (3.0 ns/pF) CL + 30 ns
tTLH = (1.5 ns/pF) CL + 15 ns
tTLH = (1.1 ns/pF) CL + 10 ns
tTLH
5.0
10
15
180
90
65
360
180
130
ns
Output Fall Time
tTHL = (1.5 ns/pF) CL + 25 ns
tTHL = (0.75 ns/pF) CL + 12.5 ns
tTHL = (0.55 ns/pF) CL + 9.5 ns
tTHL
5.0
10
15
100
50
40
200
100
80
ns
Propagation Delay Time
tPLH, tPHL = (1.7 ns/pF) CL + 30 ns
tPLH, tPHL = (0.66 ns/pF) CL + 22 ns
tPLH, tPHL = (0.50 ns/pF) CL + 15 ns
tPLH, tPHL
5.0
10
15
90
50
40
180
100
80
ns
5. The formulas given are for the typical characteristics only at 25_C.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
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