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| 型號(hào)： | MC14001BFELG |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類(lèi)： | 通用總線功能 |
| 英文描述： | B-SUFFIX SERIES CMOS GATES |
| 中文描述： | 4000/14000/40000 SERIES, QUAD 2-INPUT NOR GATE, PDSO14 |
| 封裝： | LEAD FREE, EIAJ, SO-14 |
| 文件頁(yè)數(shù)： | 7/12頁(yè) |
| 文件大小： | 134K |
| 代理商： | MC14001BFELG |
MC14001B Series
http://onsemi.com
7
TYPICAL BSERIES GATE CHARACTERISTICS (cont’d)
VOLTAGE TRANSFER CHARACTERISTICS
Figure 8. V
DD
= 5.0 Vdc
Figure 9. V
DD
= 10 Vdc
1.0
3.0
5.0
4.0
2.0
0
1.0
3.0
5.0
4.0
2.0
0
00
V
in
, INPUT VOLTAGE (Vdc)
SINGLE INPUT NAND, AND
MULTIPLE INPUT NOR, OR
SINGLE INPUT NOR, OR
MULTIPLE INPUT NAND, AND
SINGLE INPUT NAND, AND
MULTIPLE INPUT NOR, OR
SINGLE INPUT NOR, OR
MULTIPLE INPUT NAND, AND
2.0
6.0
10
8.0
4.0
2.0
6.0
10
8.0
4.0
V
in
, INPUT VOLTAGE (Vdc)
V
o
V
o
Figure 10. V
DD
= 15 Vdc
00
SINGLE INPUT NAND, AND
MULTIPLE INPUT NOR, OR
SINGLE INPUT NOR, OR
MULTIPLE INPUT NAND, AND
2.0
6.0
10
8.0
4.0
2.0
6.0
10
8.0
4.0
V
in
, INPUT VOLTAGE (Vdc)
12
14
16
V
o
DC NOISE MARGIN
The DC noise margin is defined as the input voltage range
from an ideal “1” or “0” input level which does not produce
output state change(s). The typical and guaranteed limit
values of the input values V
IL
and V
IH
for the output(s) to
be at a fixed voltage V
O
are given in the Electrical
Characteristics table. V
IL
and V
IH
are presented graphically
in Figure 11.
Guaranteed minimum noise margins for both the “1” and
“0” levels =
1.0 V with a 5.0 V supply
2.0 V with a 10.0 V supply
2.5 V with a 15.0 V supply
Figure 11. DC Noise Immunity
V
out
V
O
V
O
V
IL
0
V
IH
V
in
V
DD
V
DD
V
out
V
O
V
O
V
IL
0
V
IH
V
in
V
DD
V
DD
(a) Inverting Function
(b) NonInverting Function
V
SS
= 0 VOLTS DC
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