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參數(shù)資料
| 型號： | MC12U128DACA-2QC00 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | Dual Voltage MultiMediaCard Specification |
| 中文描述： | 雙電壓多媒體卡規(guī)格 |
| 文件頁數(shù)： | 43/64頁 |
| 文件大?。?/td> | 1385K |
| 代理商： | MC12U128DACA-2QC00 |
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MultiMediaCard
TM
All timing diagrams use the following schematics and abbreviations:
S
Start bit (= ‘0’)
T
Transmitter bit (Host = ‘1’, Card = ‘0’)
P
One-cycle pull-up (= ‘1’)
E
End bit (=1)
Z
High impedance state (-> = ‘1’)
D
Data bits
*
Repetition
CRC
Cyclic redundancy check bits (7 bits for command or
response, 16 bits for block data)
Card active
Host active
The difference between the P-bit and Z-bit is that a P-bit is actively driven to HIGH by the card
respectively host output driver, while Z-bit is driven to (respectively kept) HIGH by the pull-up resistors
R
CMD
respectively R
DAT
. Actively driven P-bits are less sensitive to noise superposition.
Timing Values
Min
Max
NCR
2
64
NID
5
5
10*(TAAC*Fop+1
00*NSAC)
NRC
8
--
NCC
8
--
NWR
2
--
NST
2
2
The host command and the card response are clocked out with the rising edge of the host clock. The
delay between host command and card response is NCR clock cycles. The following timing diagram is
relevant for host command CMD3 :
Unit
Clock cycles
Clock cycles
NAC
2
Clock cycles
Clock cycles
Clock cycles
Clock cycles
Clock cycles
Command Response Timing
(Identification Mode)
There is just one Z bit period followed by P bits pushed up by the responding card. The following timing
diagram is relevalent for all host commands followed by a response, except CMD1,CMD2 and CMD3 :
Command Response Timing
(Data Transfer Mode)
43
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| MC12U128HACA | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:MultiMediaCard Specification |
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| MC12U128HACC-0QC00 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:MultiMediaCard Specification |
| MC12U128HAFA-0QC00 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:MultiMediaCard Specification |
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