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參數(shù)資料
| 型號： | MC12439FNR2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 800 MHz, OTHER CLOCK GENERATOR, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 6/11頁 |
| 文件大?。?/td> | 128K |
| 代理商： | MC12439FNR2 |
4
MC12439
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
391
Figure 1. MC12439 Block Diagram
16.66MHz
S_LOAD
P_LOAD
S_DATA
S_CLOCK
XTAL1
XTAL2
OSC
4
5
PHASE
DETECTOR
28
7
7-BIT DIV M
COUNTER
LATCH
VCO
DIV N
(1, 2, 4, 8)
LATCH
400-800
MHz
FOUT
+3.3 or 5.0V
25
24
23
VCC0
LATCH
TEST
20
+3.3 or 5.0V
PLL_VCC
01
7-BIT SR
27
26
01
2-BIT SR
3-BIT SR
VCC1
+3.3 or 5.0V
M[6:0]
7
8 14
N[1:0]
2
17, 18
21
22, 19
OE
6
FREF_EXT
3
0
1
XTAL_SEL
15
PWR_DOWN
2
POWER DOWN
DIV 2
PROGRAMMING INTERFACE
Programming the device amounts to properly configuring the
internal dividers to produce the desired frequency at the
outputs. The output frequency can by represented by this
formula:
FOUT = FXTAL x M ÷ N
(1)
Where FXTAL is the crystal frequency, M is the loop divider
modulus, and N is the output divider modulus. Note that it is
possible to select values of M such that the PLL is unable to
achieve loop lock. To avoid this, always make sure that M is
selected to be 25
≤ M ≤ 50 for a 16MHz input reference.
For input references other than 16MHz, the valid M values
can be calculated from the valid VCO range of 400–800MHz.
Assuming that a 16MHz reference frequency is used, the
above equation reduces to:
FOUT = 16 x M
÷ N
Substituting the four values for N (1, 2, 4, 8) yields:
Output Frequency Range
N
FOUT
OUTPUT FREQUENCY RANGE
1
2
4
8
16 x M
8 x M
4 x M
2 x M
400 – 800 MHZ
200 – 400 MHZ
100 – 200 MHZ
50 – 100 MHZ
From these ranges, the user will establish the value of N
required, then the value of M can be calculated based on the
appropriate equation above. For example, if an output frequen-
cy of 384MHz was desired, the following steps would be taken
to identify the appropriate M and N values. 384 MHz falls within
the frequency range set by an N value of 2, so N [1:0] = 00. For
N = 2, FOUT = 8M and M = FOUT ÷ 8. Therefore, M = 384 ÷ 8 =
48, so M[8:0] = 0110000.
For input reference frequencies other than 16MHz, the set of
appropriate equations can be deduced from equation 1. For
computer applications, another useful frequency base would be
16.666MHz. From this reference, one can generate a family of
output frequencies at multiples of the 33.333 MHz PCI clock. As
an example, to generate a 533.333MHz clock from a
16.666MHz reference, the following M and N values would be
used:
FOUT = 16.666 x M
÷ N
Let N = 1, M = 533.333
÷ 16.666 = 32
The value for M falls within the constraints set for PLL stability
(400
÷16.666 ≤ M ≤ 800÷16.666; 24 ≤ M ≤ 48), therefore N[1:0]
= 11 and M[6:0} = 0100000. If the value for M fell outside of the
valid range, a different N value would be selected to try to move
M in the appropriate direction.
The M and N counters can be loaded either through a parallel
or serial interface. The parallel interface is controlled via the
P_LOAD signal such that a LOW to HIGH transition will latch the
information present on the M[6:0] and N[1:0] inputs into the M
and N counters. When the P_LOAD signal is LOW, the input
latches will be transparent and any changes on the M[6:0] and
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