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參數(shù)資料
| 型號(hào)： | MC10EP56DTG |
| 廠商： | ON Semiconductor |
| 文件頁(yè)數(shù)： | 9/11頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC MUX 2:1 DUAL DIFF 20TSSOP |
| 標(biāo)準(zhǔn)包裝： | 75 |
| 系列： | 10EP |
| 類型： | 差分?jǐn)?shù)字多路復(fù)用器 |
| 電路： | 2 x 2:1 |
| 獨(dú)立電路： | 1 |
| 電壓電源： | 雙電源 |
| 電源電壓： | 3 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-TSSOP |
| 包裝： | 管件 |
| 其它名稱： | MC10EP56DTGOS |
MC10EP56, MC100EP56
http://onsemi.com
7
Table 9. AC CHARACTERISTICS VCC = 0 V; VEE = 3.0 V to 5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 20)
40°C
25°C
85°C
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
fmax
Maximum Frequency
> 3
GHz
tPLH,
tPHL
Propagation Delay to
Output Differential
D to Q, Q
SEL to Q, Q
COM_SEL to Q, Q
250
340
350
450
270
360
340
360
470
300
400
500
ps
tSKEW
WithinDevice Skew (Note 21)
Device to Device Skew
50
100
200
50
100
200
50
100
200
ps
tJITTER
Random Clock Jitter
0.2
< 1
0.2
< 1
0.2
< 1
ps
VPP
Input Voltage Swing
(Differential Configuration)
150
800
1200
150
800
1200
150
800
1200
mV
tr
tf
Output Rise/Fall Times
Q, Q
(20% 80%)
70
120
170
80
130
180
100
150
230
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
20.Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC 2.0 V.
21.Skew is measured between outputs under identical transitions. Duty cycle skew is defined only for differential operation when the delays
are measured from the cross point of the inputs to the cross point of the outputs.
Figure 2. Fmax/Jitter @ 255C
FREQUENCY (GHz)
1
2
3
4
5
6
7
8
(JITTER)
9
3.3 V
V
O
U
Ta
mplitude
(mVpp)
JITTER
OUT
ps
(RMS)
10
800
1000
600
400
200
1.0
1.5
2.0
2.5
3.0
0
5 V
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D Termination of ECL Logic Devices.)
Driver
Device
Receiver
Device
QD
Q
D
Zo = 50 W
50 W
VTT
VTT = VCC 2.0 V
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