參數(shù)資料
型號(hào): MC10EP445FAR2G
廠商: ON SEMICONDUCTOR
元件分類: 通用總線功能
英文描述: 3.3V/5V ECL 8−Bit Serial/Parallel Converter
中文描述: 10E SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PQFP32
封裝: LEAD FREE, LQFP-32
文件頁(yè)數(shù): 9/18頁(yè)
文件大小: 156K
代理商: MC10EP445FAR2G
MC10EP445, MC100EP445
http://onsemi.com
9
APPLICATION INFORMATION
The MC10/100EP445 is an integrated 1:8 serial to parallel
converter with two modes of operation selected by
CKSEL (Pin 7). CKSEL HIGH mode only latches data on
the rising edge of the input CLK and CKSEL LOW mode
latches data on both the rising and falling edge of the input
CLK. CKSEL LOW is the open default state. Either of the
two differential input serial data path provided for this
device, SINA and SINB, can be chosen with the SINSEL pin
(pin 25). SINA is the default input path when SINSEL pin
is left floating. Because of internal pulldowns on the input
pins, all input pins will default to logic low when left open.
The two selectable serial data paths can be used for
loopback testing as well as the bit error testing.
Upon powerup, the internal flipflops will attain a
random state. To synchronize multiple flip–flops in the
device, the Reset (pin 1) must be asserted. The reset pin will
disable the internal clock signal irrespective of the CKEN
state (CKEN disables the internal clock circuitry). The
device will grab the first stream of data after the falling edge
of RESET , followed by the falling edge of CLK , on
second rising edge of CLK in either CKSEL modes. (See
Figure 6)
CLK
RESET
PCLK
RESET
(Asynchronous Reset)
RESET
(Synchronous ENABLE)
Figure 6. Reset Timing Diagram
相關(guān)PDF資料
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