• 參數(shù)資料
    型號: MC10EP35D
    廠商: ON SEMICONDUCTOR
    元件分類: 通用總線功能
    英文描述: JK Flip Flop
    中文描述: 10E SERIES, POSITIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO8
    封裝: SOIC-8
    文件頁數(shù): 1/8頁
    文件大小: 81K
    代理商: MC10EP35D
    Semiconductor Components Industries, LLC, 1999
    September, 1999 – Rev. 1.0
    1
    Publication Order Number:
    MC10EP35/D
    The MC10EP35 is a higher speed/low voltage version of the EL35
    JK flip flop. The J/K data enters the master portion of the flip flop
    when the clock is LOW and is transferred to the slave, and thus the
    outputs, upon a positive transition of the clock. The reset pin is
    asynchronous and is activated with a logic HIGH.
    300ps Propagation Delay
    High Bandwidth to 3 GHz Typical
    High Bandwidth Output Transistors
    PECL mode: 3.0V to 5.5V VCC with VEE = 0V
    ECL mode: 0V VCC with VEE = –3.0V to –5.5V
    75k Internal Input Pulldown Resistors
    Q Output will default LOW with inputs open or at VEE
    ESD Protection: >4KV HBM, >200V MM
    Moisture Sensitivity Level 1, Indefinite Time Out of Drypack.
    For Additional Information, See Application Note AND8003/D
    Flammability Rating: UL–94 code V–0 @ 1/8”,
    Oxygen Index 28 to 34
    Transistor Count = 77 devices
    1
    2
    3
    4
    5
    6
    7
    8
    Q
    VEE
    VCC
    Figure 1. 8–Lead Pinout
    (Top View)
    and Logic Diagram
    K
    Q
    CLK
    RESET
    J
    J
    K
    R
    Flip Flop
    SO–8
    D SUFFIX
    CASE 751
    PIN DESCRIPTION
    PIN
    CLK
    J, K
    ECL Signal Inputs
    FUNCTION
    ECL Clock Inputs
    http://onsemi.com
    RESET
    ECL Asynchronous Reset
    Q, Q
    ECL Data Outputs
    TRUTH TABLE
    J
    L
    L
    H
    H
    X
    K
    L
    H
    L
    H
    X
    RESET
    L
    L
    L
    L
    H
    CLK
    Z
    Z
    Z
    Z
    X
    Qn+1
    Qn
    L
    H
    Qn
    L
    Z = LOW to HIGH Transition
    MARKING DIAGRAM
    Device
    Package
    Shipping
    ORDERING INFORMATION
    MC10EP35D
    SOIC
    98 Units/Rail
    MC10EP35DR2
    SOIC
    2500 Tape & Reel
    HEP35
    1
    8
    ALYW
    1
    8
    A = Assembly Location
    L = Wafer Lot
    Y = Year
    W = Work Week
    *For additional information, see Application Note
    AND8002/D
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    相關(guān)代理商/技術(shù)參數(shù)
    參數(shù)描述
    MC10EP35DG 功能描述:觸發(fā)器 3.3V/5V ECL JK-Type RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel
    MC10EP35DR2 功能描述:觸發(fā)器 3.3V/5V ECL JK-Type RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel
    MC10EP35DR2G 功能描述:觸發(fā)器 3.3V/5V ECL JK-Type RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel
    MC10EP35DT 功能描述:觸發(fā)器 3.3V/5V ECL JK-Type RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel
    MC10EP35DTG 功能描述:觸發(fā)器 3.3V/5V ECL JK-Type RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel