參數(shù)資料
型號: MC10E197FN
廠商: MOTOROLA INC
元件分類: 光電元器件
英文描述: DATA SEPARATOR
中文描述: PULSE DETECTOR, PQCC28
封裝: PLASTIC, LCC-28
文件頁數(shù): 12/16頁
文件大小: 217K
代理商: MC10E197FN
MC10E197
MOTOROLA
ECLinPS and ECLinPS Lite
DL140 — Rev 4
2–12
Note, the poles P1 and P2 are now located at:
P1 = – 274kHz
P2 = –1.47MHz
And, the open loop filter unity crossover point is at 300kHz.
The gain can be adjusted by changing the value of RlA and the
value of Cd. Varying the gain by changing Cd is not
recommended because this will also move the poles, hence
affect the dynamic 2 performance of the filter.
Calculations For a 1:7 Coding Scheme
Introduction
The circuit component values are calculated for a 1:7
coding scheme employing a data rate of 20Mbit/sec. Since the
number of bits increases from two to three when the data is
encoded, the data clock is at two-thirds the frequency of the
RDCLK signal. Thus, the operating frequency for these
calculations is 30MHz. As in the case of the 2:7 coding
scheme the pole and zero positions are a function of the data
rate, hence the component values derived by these
calculations must be scaled if a different operating frequency
is used.
Again, the analysis is divided into three parts: static pole
positioning, dynamic pole positioning, and dynamic zero
positioning.
Static Poles
As in the 2:7 coding example, an MC34182D op-amp is
employed, hence the pole set is:
P1a = – 5.65 + j5.65MHz
P1b = – 5.65
j5.65MHz
and the open loop gain is:
Al = A2 = 2.48 e15V
V
Since the op-amps introduce a set of complex conjugate
poles, a total of four poles are introduced by the op-amp. In
addition, the integrator and the VCO each contribute a pole at
the origin for a total of six static poles.
Dynamic Poles
The filter input and the voltage divider sections each
contribute a dynamic pole. As stated previously, the filter input
pole should be positioned midway between the unity
crossover point and the phase detector sampling frequency.
Hence, the open loop filter input pole position is selected as:
P
*
1 = –1.1MHz
The voltage divider pole is set approximately one octave
higher than the filter input pole. Thus, the open loop voltage
divider pole position is selected as:
P
*
2 = – 2.28MHz
Dynamic Zero
Finally, the zero is positioned much less than one decade
before the crossover frequency; for this design the zero is
placed at:
z = – 311Hz
Once the dynamic pole and zero positions have been
determined, the phase margin is determined using a Bode
plot; if the phase margin is not sufficient, the dynamic poles
may be moved to improve the phase margin. Finally, a root
locus analysis is performed to obtain the optimum closed loop
pole positions for the dynamic characteristics of interest.
Component Values
Having determined the closed loop pole and zero positions
the component values are calculated. From the root locus
analysis the dynamic pole and zero positions are:
P1 = – 541kHz
P2 = – 2.73MHz
z = – 311Hz
Filter Input Subsection
Rearranging Equation 4
CIN =
1
2
π
R1
p1
and substituting 541kHz for the pole position and 1.0k
for
the resistor value yields:
CIN = 294 pF
Augmenting Integrator Subsection
Rearranging Equation 6
RA =
1
2
π
z
CA
and substituting 311Hz for the zero position and 0.1
μ
F for the
capacitor value yields:
RA = 5.11k
From Equation 7 the value for the other resistors associated
with the integrator op-amp are set equal to RA:
RlA = RA = 5.11k
相關(guān)PDF資料
PDF描述
MC10E197 DATA SEPARATOR
MC10EL32D Dual 1A Current-Limited, Power-Distribution Switches 8-MSOP-PowerPAD -40 to 85
MC10EL32 Dual 1A Current-Limited, Power-Distribution Switches 8-SOIC -40 to 85
MC100EL32D ±2 Divider
MC10EL33D ±4 Divider
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