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參數(shù)資料
| 型號(hào)： | MC10E1652FN |
| 廠商： | MOTOROLA INC |
| 元件分類(lèi)： | 通用總線功能 |
| 英文描述： | DUAL ECL OUTPUT COMPARATOR WITH LATCH |
| 中文描述： | MAGNITUDE COMPARATOR, PQCC20 |
| 封裝： | PLASTIC, LCC-20 |
| 文件頁(yè)數(shù)： | 3/7頁(yè) |
| 文件大?。?/td> | 140K |
| 代理商： | MC10E1652FN |
MC10E1652
2–3
MOTOROLA
ECLinPS and ECLinPS Lite
DL140 — Rev 4
Figure 2. Hysteresis Programming Voltage
Figure 1. Typical Hysteresis Curve
40
30
20
10
0
–0.2
–0.8
–1.0
–1.2
–1.4
–1.6
–1.8
–20 –16 –12
–8
–4
Vref
4
8
12
16
20
–0.1
0.0
0.1
0.2
0.3
0.4
0.5
Vin, DIFFERENTIAL INPUT VOLTAGE (mV)
PROGRAMMING VOLTAGE (VOLTAGE ABOVE VEE)
Q
H
HYSTERESIS
T = 0
°
C
T =
85
°
C
T =
25
°
C
AC CHARACTERISTICS
(VEE = –5.2 V
±
5%; VCC = +5.0 V
±
5%)
0
°
C
25
°
C
85
°
C
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
Condition
tPLH
tPHL
Propagation Delay to Output
V to Q
LEN to Q
600
400
750
575
900
750
625
400
775
575
925
750
700
500
850
650
1050
850
ps
1
ts
Setup Time
V
450
300
450
300
550
350
ps
th
Enable Hold Time
V
–50
–250
–50
–250
–100
–250
ps
tpw
Minimum Pulse Width
LEN
400
400
400
ps
tskew
TDE
Within Device Skew
15
15
15
ps
2
Delay Dispersion
(ECL Levels)
100
60
ps
3, 4
3, 5
TDL
Delay Dispersion
(TTL Levels)
350
100
ps
6, 7
5, 6
tr
tf
Rise/Fall Times
20-80%
225
325
475
225
325
475
250
375
500
ps
1. The propagation delay is measured from the crosspoint of the input signal and the threshold value to the crosspoint of the Q and Q output signals.
For propagation delay measurements the threshold level (VTHR) is centered about an 850 mV input logic swing with a slew rate of 0.75 V/NS.
There is an insignificant change in the propagation delay over the input common mode range.
2. tskew is the propagation delay skew between comparator A and comparator B for a particular part under identical input conditions.
3. Refer to Figure 4 and note that the input is at 850 mV ECL levels with the input threshold range between the 20% and 80% points. The delay
is measured from the crosspoint of the input signal and the threshold value to the crosspoint of the Q and Q output signals.
4. The slew rate is 0.25 V/NS for input rising edges.
5. The slew rate is 0.75 V/NS for input rising edges.
6. Refer to Figure 5 and note that the input is at 2.5 V TTL levels with the input threshold range between the 20% and 80% points. The delay is
measured from the crosspoint of the input signal and the threshold value to the crosspoint of the Q and Q output signals.
7. The slew rate is 0.3 V/NS for input rising edges.
APPLICATIONS INFORMATION
The timing diagram (Figure 3) is presented to illustrate the
MC10E1652’s compare and latch features. When the signal
on the LEN pin is at a logic high level, the device is operating
in the “compare mode,” and the signal on the input arrives at
the output after a nominal propagation delay (tPHL, tPLH). The
input signal must be asserted for a time, ts, prior to the
negative going transition on LEN and held for a time, th, after
the LEN transition. After time th, the latch is operating in the
“l(fā)atch mode,” thus transitions on the input do not appear at
the output. The device continues to operate in the “l(fā)atch
mode” until the latch is asserted once again. Moreover, the
LEN pulse must meet the minimum pulse width (tpw)
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