
Semiconductor Components Industries, LLC, 2006
November, 2006 Rev. 7
1
Publication Order Number:
MC10E143/D
MC10E143, MC100E143
5VECL 9-Bit Hold Register
Description
The MC10E/100E143 is a 9-bit holding register, designed with
byte-parity applications in mind. The E143 holds current data or loads
new data, with the nine inputs D0 D8 accepting parallel input data.
The SEL (Select) input pin is used to switch between the two modes
of operation HOLD and LOAD. Input data is accepted by the
registers a set-up time before the positive going edge of CLK1 or
CLK2. A HIGH on the Master Reset pin (MR) asynchronously resets
all the registers to zero.
The 100 Series contains temperature compensation.
Features
700 MHz Min. Operating Frequency
9-Bit for Byte-Parity Applications
Asynchronous Master Reset
Dual Clocks
PECL Mode Operating Range: VCC= 4.2 V to 5.7 V
with VEE= 0 V
NECL Mode Operating Range: VCC= 0 V
with VEE = 4.2 V to 5.7 V
Internal Input 50 kW Pulldown Resistors
ESD Protection: Human Body Model; > 2 kV,
Machine Model; > 200 V
Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test
Moisture Sensitivity Level:
Pb = 1
PbFree = 3
For Additional Information, see Application Note AND8003/D
Flammability Rating: UL 94 V0 @ 0.125 in,
Oxygen Index: 28 to 34
Transistor Count = 484 devices
PbFree Packages are Available*
*For additional information on our PbFree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
MARKING DIAGRAM*
xxx
= 10 or 100
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
G
= PbFree Package
PLCC28
FN SUFFIX
CASE 776
MCxxxE143FNG
AWLYYWW
1
http://onsemi.com
*For additional marking information, refer to
Application Note AND8002/D.
See detailed ordering and shipping information in the package
ORDERING INFORMATION