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參數(shù)資料
| 型號(hào)： | MC10E016 |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 通用總線功能 |
| 英文描述： | 8-BIT SYNCHRONOUS BINARY UP COUNTER |
| 中文描述： | 8位同步二進(jìn)制加法計(jì)數(shù)器 |
| 文件頁(yè)數(shù)： | 5/8頁(yè) |
| 文件大小： | 161K |
| 代理商： | MC10E016 |
MC10E016 MC100E016
2–5
MOTOROLA
ECLinPS and ECLinPS Lite
DL140 — Rev 4
Applications Information
(continued)
Note that this assumes the trace delay between the TC
outputs and the CE inputs are negligible. If this is not
the case estimates of these delays need to be added to
the calculations.
Programmable Divider
The E016 has been designed with a control pin which
makes it ideal for use as an 8-bit programmable divider. The
TCLD pin (load on terminal count) when asserted reloads the
data present at the parallel input pin (Pn’s) upon reaching
terminal count (an all 1s state on the outputs). Because this
feedback is built internal to the chip, the programmable
division operation will run at very nearly the same frequency
as the maximum counting frequency of the device. Figure 2
below illustrates the input conditions necessary for utilizing the
E016 as a programmable divider set up to divide by 113.
H
L
H
H
L
L
L
H
H
H
H
TC
PE
CE
TCLD
CLK
P7
P6
P4
P3
P2
P1
P0
P5
Q7
Q6
Q4
Q3
Q2
Q1
Q0
Q5
Figure 2. Mod 2 to 256 Programmable Divider
To determine what value to load into the device to
accomplish the desired division, the designer simply subtracts
the binary equivalent of the desired divide ratio from the binary
value for 256. As an example for a divide ratio of 113:
Pn’s = 256 – 113 = 8F16 = 1000 1111
where:
P0 = LSB and P7 = MSB
Forcing this input condition as per the setup in Figure 2 will
result in the waveforms of Figure 3. Note that the TC output is
used as the divide output and the pulse duration is equal to a
Table 1. Preset Values for Various Divide Ratios
Divide
Ratio
Preset Data Inputs
P7
P6
P5
P4
P3
P2
P1
P0
2
3
4
5
H
H
H
H
H
H
H
L
L
L
H
H
H
H
L
L
L
L
L
L
H
H
H
H
L
L
L
L
L
L
H
H
H
H
H
L
L
L
L
L
H
H
H
H
L
H
H
L
L
L
H
H
H
L
L
H
H
L
L
L
H
L
L
H
L
H
H
H
L
L
L
H
L
H
L
H
L
L
H
L
112
113
114
254
255
256
full clock period. For even divide ratios, twice the desired
divide ratio can be loaded into the E016 and the TC output can
feed the clock input of a toggle flip flop to create a signal
divided as desired with a 50% duty cycle.
A single E016 can be used to divide by any ratio from 2 to
256 inclusive. If divide ratios of greater than 256 are needed
multiple E016s can be cascaded in a manner similar to that
already discussed. When E016s are cascaded to build larger
dividers the TCLD pin will no longer provide a means for
loading on terminal count. Because one does not want to
reload the counters until all of the devices in the chain have
reached terminal count, external gating of the TC pins must be
used for multiple E016 divider chains.
PE
Clock
TC
Load
DIVIDE BY 113
Load
1001 0000
1001 0001
1111 1100
1111 1101
1111 1110
1111 1111
Figure 3. Divide by 113 E016 Programmable Divider Waveforms
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| MC10E016FIN | 制造商:ON Semiconductor 功能描述: |
| MC10E016FN | 功能描述:計(jì)數(shù)器移位寄存器 5V ECL 8-Bit Binary RoHS:否 制造商:Texas Instruments 計(jì)數(shù)器類型: 計(jì)數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時(shí)間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
| MC10E016FNG | 功能描述:計(jì)數(shù)器移位寄存器 5V ECL 8-Bit Binary Up Synchronous RoHS:否 制造商:Texas Instruments 計(jì)數(shù)器類型: 計(jì)數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時(shí)間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
| MC10E016FNG | 制造商:ON Semiconductor 功能描述:Binary Counter Logic IC |
| MC10E016FNR2 | 功能描述:計(jì)數(shù)器移位寄存器 5V ECL 8-Bit Binary RoHS:否 制造商:Texas Instruments 計(jì)數(shù)器類型: 計(jì)數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時(shí)間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
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