參數(shù)資料
型號(hào): MC10211
廠商: Motorola, Inc.
英文描述: Dual 3-Input/3-Output NOR Gate
中文描述: 雙3-Input/3-Output或非門
文件頁(yè)數(shù): 1/5頁(yè)
文件大?。?/td> 102K
代理商: MC10211
SEMICONDUCTOR TECHNICAL DATA
3–187
REV 5
Motorola, Inc. 1996
3/93
The MC10211 is designed to drive up to six transmission lines simul–
taneously. The multiple outputs of this device also allow the wire “OR”–ing of
several levels of gating for minimization of gate and package count.
The ability to control three parallel lines with minimum propagation delay
from a single point makes the MC10211 particularly useful in clock distribution
applications where minimum clock skew is desired.
PD= 160 mW typ/pkg (No Loads)
tpd= 1.5 ns typ (All Output Loaded)
tr, tf= 1.5 ns typ (20%–80%)
LOGIC DIAGRAM
VCC1= PIN 1, 15
VCC2= PIN 16
VEE= PIN 8
12
13
14
11
10
9
2
3
4
7
6
5
DIP
PIN ASSIGNMENT
VCC1
AOUT
AOUT
AOUT
AIN
AIN
AIN
VEE
VCC2
VCC1
BOUT
BOUT
BOUT
BIN
BIN
BIN
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–36 of the Motorola MECL Data
Book (DL122/D).
L SUFFIX
CERAMIC PACKAGE
CASE 620–10
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
FN SUFFIX
PLCC
CASE 775–02
相關(guān)PDF資料
PDF描述
MC10211L Dual 3-Input/3-Output NOR Gate
MC10211P Dual 3-Input/3-Output NOR Gate
MC10212FN Hex Buffers/Drivers With Open-Collector High-Voltage Outputs 14-CDIP -55 to 125
MC10212P High Speed Dual 3-Input/3-Output OR/NOR Gate
MC10212L Hex Buffers/Drivers With Open-Collector High-Voltage Outputs 14-CFP -55 to 125
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MC10211LD 制造商:Motorola Inc 功能描述:Logic Circuit, Dual 3-Input NOR, 16 Pin, Ceramic, DIP
MC10211LDS 制造商:Motorola Inc 功能描述: 制造商:Motorola Inc 功能描述:IC,LOGIC GATE,DUAL 3-INPUT NOR,ECL10,DIP,16PIN,CERAMIC
MC10211P 制造商:Rochester Electronics LLC 功能描述:- Bulk