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參數(shù)資料
| 型號： | MC10192L |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | 10K SERIES, QUAD 2-BIT DRIVER, COMPLEMENTARY OUTPUT, CDIP16 |
| 封裝： | CERAMIC, DIP-16 |
| 文件頁數(shù)： | 1/4頁 |
| 文件大小： | 82K |
| 代理商： | MC10192L |
Semiconductor Components Industries, LLC, 2002
January, 2002 – Rev. 7
1
Publication Order Number:
MC10192/D
MC10192
Quad Bus Driver
The MC10192 contains four line drivers with complementary
outputs. Each driver has a Data (D) input and shares an Enable (E)
input with another driver. The two driver outputs are the uncommitted
collectors of a pair of NPN transistors operating as a current switch.
Each driver accepts 10K MECL input signals and provides a nominal
signal swing of 800 mV across a 50
load at each output collector.
Outputs can drive higher values of load resistance, provided that the
combination of IR drop and load return voltage VLR does not cause an
output collector to go more negative than –2.4 V with respect to VCC.
To avoid output transistor breakdown, the load return voltage should
not be more positive than +5.5 V with respect to VCC. When the E
input is high, both output transistors of a driver are nonconducting.
When not used, the E inputs, as well as the D inputs, may be left open.
Open Collector Outputs Drive Terminated Lines or
Transformers
50 kW Input Pulldown Resistors on All Inputs (Unused
Inputs May Be Left Open)
Power Dissipation = 575 mW typ/pkg (No Load)
Propagation Delay = 3.5 ns typ (E — Output)
3.0 ns typ (D — Output)
LOGIC DIAGRAM
VCC = PIN 16
VEE = PIN 8
E1 7
D1
D2
D3
D4
E2
5
6
10
11
9
3
4
1
2
15
14
13
12
Z1
Z2
Z3
Z4
TRUTH TABLE
Inputs
Output
E
D
Z
H
X
H
L
H
L
H
Note: Unused outputs must be terminated
to VCC for proper operation.
http://onsemi.com
Device
Package
Shipping
ORDERING INFORMATION
MC10192L
CDIP–16
25 Units / Rail
MC10192P
PDIP–16
25 Units / Rail
MC10192FN
PLCC–20
46 Units / Rail
MARKING
DIAGRAMS
1
16
A
= Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
CDIP–16
L SUFFIX
CASE 620
MC10192L
AWLYYWW
PDIP–16
P SUFFIX
CASE 648
PLCC–20
FN SUFFIX
CASE 775
10192
AWLYYWW
1
16
MC10192P
AWLYYWW
DIP PIN ASSIGNMENT
Z2
Z1
D1
D2
E1
VEE
VCC
Z3
Z4
D4
D3
E2
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables
on page 18 of the ON Semiconductor MECL Data Book
(DL122/D).
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