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參數資料
| 型號： | MC10188P |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 門電路 |
| 英文描述： | 10K SERIES, HEX 1-INPUT NON-INVERT GATE, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁數： | 2/4頁 |
| 文件大小： | 82K |
| 代理商： | MC10188P |
MC10188
http://onsemi.com
2
ELECTRICAL CHARACTERISTICS
Test Limits
Pin
Under
–30
°C
+25
°C
+85
°C
Characteristic
Symbol
Under
Test
Min
Max
Min
Max
Min
Max
Unit
Power Supply Drain Current
IE
8
46
42
46
mAdc
Input Current
IinH
5
425
265
Adc
IinH
9
460
290
Adc
Output Voltage
Logic 1
VOH
2
–1.060
–0.890
–0.960
–0.810
–0.890
–0.700
Vdc
Output Voltage
Logic 0
VOL
2
–1.890
–1.675
–1.850
–1.650
–1.825
–1.615
Vdc
Threshold Voltage
Logic 1
VOHA
2
–1.080
–0.980
–0.910
Vdc
Threshold Voltage
Logic 0
VOLA
2
–1.655
–1.630
–1.595
Vdc
Switching Times
(50
Load)
ns
Propagation Delay
Enable
Data
tPHL
tPLH
2
1.1
1.0
3.9
3.3
1.1
1.0
3.5
2.9
1.1
1.0
3.9
3.3
Rise/Fall Time
(20 to 80%)
tTLH
tTHL
2
1.1
3.7
1.1
3.3
1.1
3.7
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts)
@ Test Temperature
VIHmax
VILmin
VIHAmin
VILAmax
VEE
–30
°C
–0.890
–1.890
–1.205
–1.500
–5.2
+25
°C
–0.810
–1.850
–1.105
–1.475
–5.2
+85
°C
–0.700
–1.825
–1.035
–1.440
–5.2
Pin
Under
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
(V
)
Characteristic
Symbol
Under
Test
VIHmax
VILmin
VIHAmin
VILAmax
VEE
(VCC)
Gnd
Power Supply Drain Current
IE
8
1, 16
Input Current
IinH
5
8
1, 16
IinH
9
8
1, 16
Output Voltage
Logic 1
VOH
2
5
8
1, 16
Output Voltage
Logic 0
VOL
2
9
8
1, 16
Threshold Voltage
Logic 1
VOHA
2
5
8
1, 16
Threshold Voltage
Logic 0
VOLA
2
5
8
1, 16
Switching Times
(50
Load)
Pulse In
Pulse Out
–3.2 V
+2.0 V
Propagation Delay
Enable
Data
tPHL
tPLH
2
9
5
2
8
1, 16
Rise/Fall Time
(20 to 80%)
tTLH
tTHL
2
5
2
8
1, 16
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.
Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the
same manner.
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