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參數(shù)資料
| 型號(hào)： | MC10173FN |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 鎖存器 |
| 英文描述： | 10K SERIES, LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, PQCC20 |
| 封裝： | PLASTIC, LCC-20 |
| 文件頁(yè)數(shù)： | 3/8頁(yè) |
| 文件大小： | 108K |
| 代理商： | MC10173FN |
MC10173
http://onsemi.com
3
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts)
@ Test Temperature
VIHmax
VILmin
VIHAmin
VILAmax
VEE
–30
°C
–0.890
–1.890
–1.205
–1.500
–5.2
+25
°C
–0.810
–1.850
–1.105
–1.475
–5.2
+85
°C
–0.700
–1.825
–1.035
–1.440
–5.2
Pin
Under
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
(V
)
Characteristic
Symbol
Under
Test
VIHmax
VILmin
VIHAmin
VILAmax
VEE
(VCC)
Gnd
Power Supply Drain Current
IE
8
16
Input Current
5
6
7
9
5
6
7
9
8
16
IinL
All
*
8
16
Output Voltage
Logic 1
VOH
1
2
6, 9
5
7
8
16
Output Voltage
Logic 0
VOL
1
2
9
7
8
16
Threshold Voltage
Logic 1
VOHA
1
2
9
7
6
5
8
16
Threshold Voltage
Logic 0
VOLA
1
2
9
7
6
5
8
16
Switching Times
(50
Load)
+1.11V
+0.31V
Pulse In
Pulse Out
–3.2 V
+2.0 V
Propagation Delay
Data Input
t6+1+
t6–1–
t5+1+
t5–1–
1
9
7
6
5
1
8
16
Clock Input
t7–1+
t7–1–
1
5, 7
1
8
16
Select Input
t9+1+
t9+1–
t9–1+
t9–1–
1
6
5
6
7
9
1
8
16
Setup TIme
Data Input
Select Input
tsetup
1
6
5, 7
7, 9
1
8
16
Hold TIme
Data Input
Select Input
thold
1
6
5, 7
7, 9
1
8
16
Rise Time
(20 to 80%)
t+
1
5
7
1
8
16
Fall Time
(20 to 80%)
t–
1
7
1
8
16
*VILmin applied to each input pin, one at a time.
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.
Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the
same manner.
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