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參數(shù)資料
| 型號(hào)： | MC10141P |
| 廠商： | MOTOROLA INC |
| 元件分類(lèi)： | 通用總線功能 |
| 英文描述： | Replaced by SN54LS193 : Synchronous 4-Bit Up/Down Counters (Dual Clock With Clear) 16-CDIP -55 to 125 |
| 中文描述： | 10K SERIES, 4-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDIP16 |
| 封裝： | 648-08 |
| 文件頁(yè)數(shù)： | 1/6頁(yè) |
| 文件大小： | 123K |
| 代理商： | MC10141P |
SEMICONDUCTOR TECHNICAL DATA
3–46
REV 5
Motorola, Inc. 1996
3/93
The MC10141 is a four–bit universal shift register which performs shift left, or
shift right, serial/parallel in, and serial/parallel out operations with no external
gating. Inputs S1 and S2 control the four possible operations of the register
without external gating of the clock. The flip–flops shift information on the
positive edge of the clock. The four operations are stop shift, shift left, shift right,
and parallel entry of data. The other six inputs are all data type inputs; four for
parallel entry data, and one for shifting in from the left (DL) and one for shifting
in from the right (DR).
PD= 425 mW typ/pkg (No Load)
fShift= 200 MHz typ
tr, tf= 2.0 ns typ (20%–80%)
LOGIC DIAGRAM
VCC1= PIN 1
VCC2= PIN 16
VEE= PIN 8
Parallel Enter
Shift Right
Shift Left
Hold
D Q
C
1 of 4
Decoder
D3
DL
S1
DR
C
Q3
S2
D2
D1
D0
Q2
Q1
Q0
D Q
C
D Q
C
D Q
C
TRUTH TABLE
SELECT
OUTPUTS
S1
L
L
H
H
S2
L
H
L
H
OPERATING MODE
Parallel Entry
Shift Right*
Shift Left*
Stop Shift
Q0n+1
D0
Q1n
DL
Q0n
Q1n+1
D1
Q2n
Q0n
Q1n
Q2n+1
D2
Q3n
Q1n
Q2n
Q3n+1
D3
DR
Q2n
Q3n
*Outputs as exist after pulse appears at “C” input with input conditions as
shown. (Pulse = Positive transition of clock input).
DIP
PIN ASSIGNMENT
VCC1
Q2
Q3
C
DR
D3
S2
VEE
VCC2
Q1
Q0
DL
D0
D1
S1
D2
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
L SUFFIX
CERAMIC PACKAGE
CASE 620–10
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
FN SUFFIX
PLCC
CASE 775–02
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
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