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參數(shù)資料
| 型號(hào)： | MC10133FN |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 鎖存器 |
| 英文描述： | 10K SERIES, DUAL HIGH LEVEL TRIGGERED D LATCH, TRUE OUTPUT, PQCC20 |
| 封裝： | PLASTIC, LCC-20 |
| 文件頁(yè)數(shù)： | 2/3頁(yè) |
| 文件大?。?/td> | 55K |
| 代理商： | MC10133FN |
MC10133
http://onsemi.com
310
ELECTRICAL CHARACTERISTICS
Test Limits
Pin
Under
–30
°C
+25
°C
+85
°C
Characteristic
Symbol
Under
Test
Min
Max
Min
Typ
Max
Min
Max
Unit
Power Supply Drain Current
IE
8
82
75
82
mAdc
Input Current
IinH
3
4
5
13
390
425
560
245
265
350
245
265
350
Adc
IinL
3
0.5
0.3
Adc
Output Voltage
Logic 1
VOH
2
–1.060
–0.890
–0.960
–0.810
–0.890
–0.700
Vdc
Output Voltage
Logic 0
VOL
2
–1.890
–1.675
–1.850
–1.650
–1.825
–1.615
Vdc
Threshold Voltage
Logic 1
VOHA
2
[
2
]
2
]
2
–1.080
–0.980
–0.910
Vdc
Threshold Voltage
Logic 0
VOLA
2
[
2
]
2
]
–1.655
–1.630
–1.595
Vdc
Switching Times (50
Load)
ns
Propagation Delay
t3+2+
t4+2+
t5–2+
tsetup
thold
2
3
1.0
2.5
1.5
5.6
5.4
3.2
1.0
2.5
1.5
4.0
2.0
0.7
5.4
3.1
1.1
1.2
1.0
2.5
1.5
5.9
6.0
3.4
Rise Time
(20 to 80%)
t2+
2
1.0
3.6
1.1
2.0
3.5
1.1
3.8
Fall Time
(20 to 80%)
t2–
2
1.0
3.6
1.1
2.0
3.5
1.1
3.8
[ Output level to be measured after a clock pulse has been applied to the clock input (Pin 4)
VIHmax
VILmin
] Data input at proper high/low level while clock pulse is high so that device latches ar proper high/low level for test. Levels are measured after
device has latched.
* Latch set to zero state before test.
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